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annotate third_party/luajit/src/lj_emit_arm.h @ 178:94705b5986b3

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[ThirdParty] Added WRK and luajit for load testing.
author MrJuneJune <me@mrjunejune.com>
date Thu, 22 Jan 2026 20:10:30 -0800
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children
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178
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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1 /*
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2 ** ARM instruction emitter.
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3 ** Copyright (C) 2005-2023 Mike Pall. See Copyright Notice in luajit.h
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4 */
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5
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6 /* -- Constant encoding --------------------------------------------------- */
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7
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8 static uint8_t emit_invai[16] = {
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9 /* AND */ (ARMI_AND^ARMI_BIC) >> 21,
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10 /* EOR */ 0,
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11 /* SUB */ (ARMI_SUB^ARMI_ADD) >> 21,
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12 /* RSB */ 0,
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13 /* ADD */ (ARMI_ADD^ARMI_SUB) >> 21,
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14 /* ADC */ (ARMI_ADC^ARMI_SBC) >> 21,
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15 /* SBC */ (ARMI_SBC^ARMI_ADC) >> 21,
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16 /* RSC */ 0,
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17 /* TST */ 0,
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18 /* TEQ */ 0,
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19 /* CMP */ (ARMI_CMP^ARMI_CMN) >> 21,
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20 /* CMN */ (ARMI_CMN^ARMI_CMP) >> 21,
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21 /* ORR */ 0,
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22 /* MOV */ (ARMI_MOV^ARMI_MVN) >> 21,
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23 /* BIC */ (ARMI_BIC^ARMI_AND) >> 21,
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24 /* MVN */ (ARMI_MVN^ARMI_MOV) >> 21
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25 };
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26
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27 /* Encode constant in K12 format for data processing instructions. */
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28 static uint32_t emit_isk12(ARMIns ai, int32_t n)
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29 {
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30 uint32_t invai, i, m = (uint32_t)n;
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31 /* K12: unsigned 8 bit value, rotated in steps of two bits. */
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32 for (i = 0; i < 4096; i += 256, m = lj_rol(m, 2))
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33 if (m <= 255) return ARMI_K12|m|i;
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34 /* Otherwise try negation/complement with the inverse instruction. */
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35 invai = emit_invai[((ai >> 21) & 15)];
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36 if (!invai) return 0; /* Failed. No inverse instruction. */
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37 m = ~(uint32_t)n;
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38 if (invai == ((ARMI_SUB^ARMI_ADD) >> 21) ||
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39 invai == (ARMI_CMP^ARMI_CMN) >> 21) m++;
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40 for (i = 0; i < 4096; i += 256, m = lj_rol(m, 2))
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41 if (m <= 255) return ARMI_K12|(invai<<21)|m|i;
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42 return 0; /* Failed. */
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43 }
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44
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45 /* -- Emit basic instructions --------------------------------------------- */
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46
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47 static void emit_dnm(ASMState *as, ARMIns ai, Reg rd, Reg rn, Reg rm)
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48 {
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49 *--as->mcp = ai | ARMF_D(rd) | ARMF_N(rn) | ARMF_M(rm);
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50 }
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51
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52 static void emit_dm(ASMState *as, ARMIns ai, Reg rd, Reg rm)
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53 {
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54 *--as->mcp = ai | ARMF_D(rd) | ARMF_M(rm);
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55 }
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56
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57 static void emit_dn(ASMState *as, ARMIns ai, Reg rd, Reg rn)
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58 {
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59 *--as->mcp = ai | ARMF_D(rd) | ARMF_N(rn);
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60 }
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61
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62 static void emit_nm(ASMState *as, ARMIns ai, Reg rn, Reg rm)
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63 {
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64 *--as->mcp = ai | ARMF_N(rn) | ARMF_M(rm);
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65 }
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66
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67 static void emit_d(ASMState *as, ARMIns ai, Reg rd)
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68 {
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69 *--as->mcp = ai | ARMF_D(rd);
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70 }
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71
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72 static void emit_n(ASMState *as, ARMIns ai, Reg rn)
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73 {
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74 *--as->mcp = ai | ARMF_N(rn);
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75 }
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76
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77 static void emit_m(ASMState *as, ARMIns ai, Reg rm)
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78 {
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79 *--as->mcp = ai | ARMF_M(rm);
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80 }
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81
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82 static void emit_lsox(ASMState *as, ARMIns ai, Reg rd, Reg rn, int32_t ofs)
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83 {
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84 lj_assertA(ofs >= -255 && ofs <= 255,
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85 "load/store offset %d out of range", ofs);
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86 if (ofs < 0) ofs = -ofs; else ai |= ARMI_LS_U;
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87 *--as->mcp = ai | ARMI_LS_P | ARMI_LSX_I | ARMF_D(rd) | ARMF_N(rn) |
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88 ((ofs & 0xf0) << 4) | (ofs & 0x0f);
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89 }
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90
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91 static void emit_lso(ASMState *as, ARMIns ai, Reg rd, Reg rn, int32_t ofs)
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92 {
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93 lj_assertA(ofs >= -4095 && ofs <= 4095,
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94 "load/store offset %d out of range", ofs);
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95 /* Combine LDR/STR pairs to LDRD/STRD. */
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96 if (*as->mcp == (ai|ARMI_LS_P|ARMI_LS_U|ARMF_D(rd^1)|ARMF_N(rn)|(ofs^4)) &&
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97 (ai & ~(ARMI_LDR^ARMI_STR)) == ARMI_STR && rd != rn &&
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98 (uint32_t)ofs <= 252 && !(ofs & 3) && !((rd ^ (ofs >>2)) & 1) &&
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99 as->mcp != as->mcloop) {
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100 as->mcp++;
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101 emit_lsox(as, ai == ARMI_LDR ? ARMI_LDRD : ARMI_STRD, rd&~1, rn, ofs&~4);
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102 return;
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103 }
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104 if (ofs < 0) ofs = -ofs; else ai |= ARMI_LS_U;
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105 *--as->mcp = ai | ARMI_LS_P | ARMF_D(rd) | ARMF_N(rn) | ofs;
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106 }
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107
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108 #if !LJ_SOFTFP
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109 static void emit_vlso(ASMState *as, ARMIns ai, Reg rd, Reg rn, int32_t ofs)
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110 {
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111 lj_assertA(ofs >= -1020 && ofs <= 1020 && (ofs&3) == 0,
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112 "load/store offset %d out of range", ofs);
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113 if (ofs < 0) ofs = -ofs; else ai |= ARMI_LS_U;
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114 *--as->mcp = ai | ARMI_LS_P | ARMF_D(rd & 15) | ARMF_N(rn) | (ofs >> 2);
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115 }
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116 #endif
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117
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118 /* -- Emit loads/stores --------------------------------------------------- */
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119
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120 /* Prefer spills of BASE/L. */
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121 #define emit_canremat(ref) ((ref) < ASMREF_L)
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122
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123 /* Try to find a one step delta relative to another constant. */
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124 static int emit_kdelta1(ASMState *as, Reg d, int32_t i)
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diff changeset
125 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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126 RegSet work = ~as->freeset & RSET_GPR;
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127 while (work) {
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128 Reg r = rset_picktop(work);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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129 IRRef ref = regcost_ref(as->cost[r]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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130 lj_assertA(r != d, "dest reg not free");
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131 if (emit_canremat(ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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132 int32_t delta = i - (ra_iskref(ref) ? ra_krefk(as, ref) : IR(ref)->i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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133 uint32_t k = emit_isk12(ARMI_ADD, delta);
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diff changeset
134 if (k) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
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diff changeset
135 if (k == ARMI_K12)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
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diff changeset
136 emit_dm(as, ARMI_MOV, d, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
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137 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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138 emit_dn(as, ARMI_ADD^k, d, r);
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139 return 1;
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140 }
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141 }
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142 rset_clear(work, r);
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MrJuneJune <me@mrjunejune.com>
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143 }
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MrJuneJune <me@mrjunejune.com>
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144 return 0; /* Failed. */
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145 }
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146
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diff changeset
147 /* Try to find a two step delta relative to another constant. */
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148 static int emit_kdelta2(ASMState *as, Reg rd, int32_t i)
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149 {
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150 RegSet work = ~as->freeset & RSET_GPR;
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151 while (work) {
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152 Reg r = rset_picktop(work);
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153 IRRef ref = regcost_ref(as->cost[r]);
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154 lj_assertA(r != rd, "dest reg %d not free", rd);
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MrJuneJune <me@mrjunejune.com>
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diff changeset
155 if (emit_canremat(ref)) {
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MrJuneJune <me@mrjunejune.com>
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diff changeset
156 int32_t other = ra_iskref(ref) ? ra_krefk(as, ref) : IR(ref)->i;
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MrJuneJune <me@mrjunejune.com>
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157 if (other) {
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158 int32_t delta = i - other;
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MrJuneJune <me@mrjunejune.com>
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diff changeset
159 uint32_t sh, inv = 0, k2, k;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
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160 if (delta < 0) { delta = (int32_t)(~(uint32_t)delta+1u); inv = ARMI_ADD^ARMI_SUB; }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
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161 sh = lj_ffs(delta) & ~1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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162 k2 = emit_isk12(0, delta & (255 << sh));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
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163 k = emit_isk12(0, delta & ~(255 << sh));
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MrJuneJune <me@mrjunejune.com>
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164 if (k) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
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165 emit_dn(as, ARMI_ADD^k2^inv, rd, rd);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
166 emit_dn(as, ARMI_ADD^k^inv, rd, r);
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167 return 1;
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168 }
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169 }
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170 }
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diff changeset
171 rset_clear(work, r);
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MrJuneJune <me@mrjunejune.com>
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diff changeset
172 }
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diff changeset
173 return 0; /* Failed. */
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MrJuneJune <me@mrjunejune.com>
parents:
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174 }
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diff changeset
175
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diff changeset
176 /* Load a 32 bit constant into a GPR. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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177 static void emit_loadi(ASMState *as, Reg rd, int32_t i)
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178 {
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MrJuneJune <me@mrjunejune.com>
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diff changeset
179 uint32_t k = emit_isk12(ARMI_MOV, i);
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180 lj_assertA(rset_test(as->freeset, rd) || rd == RID_TMP,
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181 "dest reg %d not free", rd);
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MrJuneJune <me@mrjunejune.com>
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diff changeset
182 if (k) {
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
183 /* Standard K12 constant. */
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MrJuneJune <me@mrjunejune.com>
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diff changeset
184 emit_d(as, ARMI_MOV^k, rd);
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185 } else if ((as->flags & JIT_F_ARMV6T2) && (uint32_t)i < 0x00010000u) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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diff changeset
186 /* 16 bit loword constant for ARMv6T2. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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187 emit_d(as, ARMI_MOVW|(i & 0x0fff)|((i & 0xf000)<<4), rd);
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188 } else if (emit_kdelta1(as, rd, i)) {
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diff changeset
189 /* One step delta relative to another constant. */
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diff changeset
190 } else if ((as->flags & JIT_F_ARMV6T2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
191 /* 32 bit hiword/loword constant for ARMv6T2. */
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192 emit_d(as, ARMI_MOVT|((i>>16) & 0x0fff)|(((i>>16) & 0xf000)<<4), rd);
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parents:
diff changeset
193 emit_d(as, ARMI_MOVW|(i & 0x0fff)|((i & 0xf000)<<4), rd);
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194 } else if (emit_kdelta2(as, rd, i)) {
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parents:
diff changeset
195 /* Two step delta relative to another constant. */
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
196 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
197 /* Otherwise construct the constant with up to 4 instructions. */
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parents:
diff changeset
198 /* NYI: use mvn+bic, use pc-relative loads. */
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diff changeset
199 for (;;) {
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diff changeset
200 uint32_t sh = lj_ffs(i) & ~1;
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parents:
diff changeset
201 int32_t m = i & (255 << sh);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
202 i &= ~(255 << sh);
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
203 if (i == 0) {
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
204 emit_d(as, ARMI_MOV ^ emit_isk12(0, m), rd);
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parents:
diff changeset
205 break;
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
206 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
207 emit_dn(as, ARMI_ORR ^ emit_isk12(0, m), rd, rd);
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208 }
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
209 }
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
210 }
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
211
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
212 #define emit_loada(as, rd, addr) emit_loadi(as, (rd), i32ptr((addr)))
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
213
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
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diff changeset
214 static Reg ra_allock(ASMState *as, intptr_t k, RegSet allow);
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diff changeset
215
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
216 /* Get/set from constant pointer. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
217 static void emit_lsptr(ASMState *as, ARMIns ai, Reg r, void *p)
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parents:
diff changeset
218 {
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parents:
diff changeset
219 int32_t i = i32ptr(p);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
220 emit_lso(as, ai, r, ra_allock(as, (i & ~4095), rset_exclude(RSET_GPR, r)),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
221 (i & 4095));
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
222 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
223
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
224 #if !LJ_SOFTFP
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
225 /* Load a number constant into an FPR. */
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
226 static void emit_loadk64(ASMState *as, Reg r, IRIns *ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
227 {
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parents:
diff changeset
228 cTValue *tv = ir_knum(ir);
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parents:
diff changeset
229 int32_t i;
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
230 if ((as->flags & JIT_F_VFPV3) && !tv->u32.lo) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
231 uint32_t hi = tv->u32.hi;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
232 uint32_t b = ((hi >> 22) & 0x1ff);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
233 if (!(hi & 0xffff) && (b == 0x100 || b == 0x0ff)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
234 *--as->mcp = ARMI_VMOVI_D | ARMF_D(r & 15) |
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
235 ((tv->u32.hi >> 12) & 0x00080000) |
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
236 ((tv->u32.hi >> 4) & 0x00070000) |
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
237 ((tv->u32.hi >> 16) & 0x0000000f);
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
238 return;
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
239 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
240 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
241 i = i32ptr(tv);
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
242 emit_vlso(as, ARMI_VLDR_D, r,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
243 ra_allock(as, (i & ~1020), RSET_GPR), (i & 1020));
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parents:
diff changeset
244 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
245 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
246
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
247 /* Get/set global_State fields. */
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
248 #define emit_getgl(as, r, field) \
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
249 emit_lsptr(as, ARMI_LDR, (r), (void *)&J2G(as->J)->field)
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250 #define emit_setgl(as, r, field) \
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251 emit_lsptr(as, ARMI_STR, (r), (void *)&J2G(as->J)->field)
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252
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253 /* Trace number is determined from pc of exit instruction. */
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254 #define emit_setvmstate(as, i) UNUSED(i)
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255
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diff changeset
256 /* -- Emit control-flow instructions -------------------------------------- */
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257
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258 /* Label for internal jumps. */
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diff changeset
259 typedef MCode *MCLabel;
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260
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261 /* Return label pointing to current PC. */
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262 #define emit_label(as) ((as)->mcp)
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263
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264 static void emit_branch(ASMState *as, ARMIns ai, MCode *target)
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265 {
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266 MCode *p = as->mcp;
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267 ptrdiff_t delta = (target - p) - 1;
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268 lj_assertA(((delta + 0x00800000) >> 24) == 0, "branch target out of range");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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269 *--p = ai | ((uint32_t)delta & 0x00ffffffu);
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270 as->mcp = p;
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271 }
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272
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273 #define emit_jmp(as, target) emit_branch(as, ARMI_B, (target))
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274
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275 static void emit_call(ASMState *as, void *target)
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276 {
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277 MCode *p = --as->mcp;
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278 ptrdiff_t delta = ((char *)target - (char *)p) - 8;
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279 if ((((delta>>2) + 0x00800000) >> 24) == 0) {
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280 if ((delta & 1))
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281 *p = ARMI_BLX | ((uint32_t)(delta>>2) & 0x00ffffffu) | ((delta&2) << 23);
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282 else
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283 *p = ARMI_BL | ((uint32_t)(delta>>2) & 0x00ffffffu);
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284 } else { /* Target out of range: need indirect call. But don't use R0-R3. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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285 Reg r = ra_allock(as, i32ptr(target), RSET_RANGE(RID_R4, RID_R12+1));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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286 *p = ARMI_BLXr | ARMF_M(r);
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287 }
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diff changeset
288 }
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289
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diff changeset
290 /* -- Emit generic operations --------------------------------------------- */
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diff changeset
291
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diff changeset
292 /* Generic move between two regs. */
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diff changeset
293 static void emit_movrr(ASMState *as, IRIns *ir, Reg dst, Reg src)
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294 {
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diff changeset
295 #if LJ_SOFTFP
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diff changeset
296 lj_assertA(!irt_isnum(ir->t), "unexpected FP op"); UNUSED(ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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297 #else
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diff changeset
298 if (dst >= RID_MAX_GPR) {
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diff changeset
299 emit_dm(as, irt_isnum(ir->t) ? ARMI_VMOV_D : ARMI_VMOV_S,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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diff changeset
300 (dst & 15), (src & 15));
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diff changeset
301 return;
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diff changeset
302 }
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diff changeset
303 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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diff changeset
304 if (as->mcp != as->mcloop) { /* Swap early registers for loads/stores. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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diff changeset
305 MCode ins = *as->mcp, swp = (src^dst);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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diff changeset
306 if ((ins & 0x0c000000) == 0x04000000 && (ins & 0x02000010) != 0x02000010) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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diff changeset
307 if (!((ins ^ (dst << 16)) & 0x000f0000))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
308 *as->mcp = ins ^ (swp << 16); /* Swap N in load/store. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
309 if (!(ins & 0x00100000) && !((ins ^ (dst << 12)) & 0x0000f000))
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parents:
diff changeset
310 *as->mcp = ins ^ (swp << 12); /* Swap D in store. */
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parents:
diff changeset
311 }
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diff changeset
312 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
313 emit_dm(as, ARMI_MOV, dst, src);
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diff changeset
314 }
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parents:
diff changeset
315
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parents:
diff changeset
316 /* Generic load of register with base and (small) offset address. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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diff changeset
317 static void emit_loadofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
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diff changeset
318 {
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diff changeset
319 #if LJ_SOFTFP
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diff changeset
320 lj_assertA(!irt_isnum(ir->t), "unexpected FP op"); UNUSED(ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
321 #else
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parents:
diff changeset
322 if (r >= RID_MAX_GPR)
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parents:
diff changeset
323 emit_vlso(as, irt_isnum(ir->t) ? ARMI_VLDR_D : ARMI_VLDR_S, r, base, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
324 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
325 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
326 emit_lso(as, ARMI_LDR, r, base, ofs);
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
327 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
328
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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diff changeset
329 /* Generic store of register with base and (small) offset address. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
330 static void emit_storeofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
331 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
332 #if LJ_SOFTFP
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
333 lj_assertA(!irt_isnum(ir->t), "unexpected FP op"); UNUSED(ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
334 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
335 if (r >= RID_MAX_GPR)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
336 emit_vlso(as, irt_isnum(ir->t) ? ARMI_VSTR_D : ARMI_VSTR_S, r, base, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
337 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
338 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
339 emit_lso(as, ARMI_STR, r, base, ofs);
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parents:
diff changeset
340 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
341
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
342 /* Emit an arithmetic/logic operation with a constant operand. */
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parents:
diff changeset
343 static void emit_opk(ASMState *as, ARMIns ai, Reg dest, Reg src,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
344 int32_t i, RegSet allow)
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
345 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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diff changeset
346 uint32_t k = emit_isk12(ai, i);
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parents:
diff changeset
347 if (k)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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diff changeset
348 emit_dn(as, ai^k, dest, src);
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parents:
diff changeset
349 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
350 emit_dnm(as, ai, dest, src, ra_allock(as, i, allow));
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parents:
diff changeset
351 }
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parents:
diff changeset
352
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
353 /* Add offset to pointer. */
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MrJuneJune <me@mrjunejune.com>
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diff changeset
354 static void emit_addptr(ASMState *as, Reg r, int32_t ofs)
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parents:
diff changeset
355 {
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parents:
diff changeset
356 if (ofs)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
357 emit_opk(as, ARMI_ADD, r, r, ofs, rset_exclude(RSET_GPR, r));
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parents:
diff changeset
358 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
359
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
360 #define emit_spsub(as, ofs) emit_addptr(as, RID_SP, -(ofs))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
361