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comparison third_party/luajit/src/lj_asm_arm.h @ 178:94705b5986b3

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[ThirdParty] Added WRK and luajit for load testing.
author MrJuneJune <me@mrjunejune.com>
date Thu, 22 Jan 2026 20:10:30 -0800
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177:24fe8ff94056 178:94705b5986b3
1 /*
2 ** ARM IR assembler (SSA IR -> machine code).
3 ** Copyright (C) 2005-2023 Mike Pall. See Copyright Notice in luajit.h
4 */
5
6 /* -- Register allocator extensions --------------------------------------- */
7
8 /* Allocate a register with a hint. */
9 static Reg ra_hintalloc(ASMState *as, IRRef ref, Reg hint, RegSet allow)
10 {
11 Reg r = IR(ref)->r;
12 if (ra_noreg(r)) {
13 if (!ra_hashint(r) && !iscrossref(as, ref))
14 ra_sethint(IR(ref)->r, hint); /* Propagate register hint. */
15 r = ra_allocref(as, ref, allow);
16 }
17 ra_noweak(as, r);
18 return r;
19 }
20
21 /* Allocate a scratch register pair. */
22 static Reg ra_scratchpair(ASMState *as, RegSet allow)
23 {
24 RegSet pick1 = as->freeset & allow;
25 RegSet pick2 = pick1 & (pick1 >> 1) & RSET_GPREVEN;
26 Reg r;
27 if (pick2) {
28 r = rset_picktop(pick2);
29 } else {
30 RegSet pick = pick1 & (allow >> 1) & RSET_GPREVEN;
31 if (pick) {
32 r = rset_picktop(pick);
33 ra_restore(as, regcost_ref(as->cost[r+1]));
34 } else {
35 pick = pick1 & (allow << 1) & RSET_GPRODD;
36 if (pick) {
37 r = ra_restore(as, regcost_ref(as->cost[rset_picktop(pick)-1]));
38 } else {
39 r = ra_evict(as, allow & (allow >> 1) & RSET_GPREVEN);
40 ra_restore(as, regcost_ref(as->cost[r+1]));
41 }
42 }
43 }
44 lj_assertA(rset_test(RSET_GPREVEN, r), "odd reg %d", r);
45 ra_modified(as, r);
46 ra_modified(as, r+1);
47 RA_DBGX((as, "scratchpair $r $r", r, r+1));
48 return r;
49 }
50
51 #if !LJ_SOFTFP
52 /* Allocate two source registers for three-operand instructions. */
53 static Reg ra_alloc2(ASMState *as, IRIns *ir, RegSet allow)
54 {
55 IRIns *irl = IR(ir->op1), *irr = IR(ir->op2);
56 Reg left = irl->r, right = irr->r;
57 if (ra_hasreg(left)) {
58 ra_noweak(as, left);
59 if (ra_noreg(right))
60 right = ra_allocref(as, ir->op2, rset_exclude(allow, left));
61 else
62 ra_noweak(as, right);
63 } else if (ra_hasreg(right)) {
64 ra_noweak(as, right);
65 left = ra_allocref(as, ir->op1, rset_exclude(allow, right));
66 } else if (ra_hashint(right)) {
67 right = ra_allocref(as, ir->op2, allow);
68 left = ra_alloc1(as, ir->op1, rset_exclude(allow, right));
69 } else {
70 left = ra_allocref(as, ir->op1, allow);
71 right = ra_alloc1(as, ir->op2, rset_exclude(allow, left));
72 }
73 return left | (right << 8);
74 }
75 #endif
76
77 /* -- Guard handling ------------------------------------------------------ */
78
79 /* Generate an exit stub group at the bottom of the reserved MCode memory. */
80 static MCode *asm_exitstub_gen(ASMState *as, ExitNo group)
81 {
82 MCode *mxp = as->mcbot;
83 int i;
84 if (mxp + 4*4+4*EXITSTUBS_PER_GROUP >= as->mctop)
85 asm_mclimit(as);
86 /* str lr, [sp]; bl ->vm_exit_handler; .long DISPATCH_address, group. */
87 *mxp++ = ARMI_STR|ARMI_LS_P|ARMI_LS_U|ARMF_D(RID_LR)|ARMF_N(RID_SP);
88 *mxp = ARMI_BL|((((MCode *)(void *)lj_vm_exit_handler-mxp)-2)&0x00ffffffu);
89 mxp++;
90 *mxp++ = (MCode)i32ptr(J2GG(as->J)->dispatch); /* DISPATCH address */
91 *mxp++ = group*EXITSTUBS_PER_GROUP;
92 for (i = 0; i < EXITSTUBS_PER_GROUP; i++)
93 *mxp++ = ARMI_B|((-6-i)&0x00ffffffu);
94 lj_mcode_sync(as->mcbot, mxp);
95 lj_mcode_commitbot(as->J, mxp);
96 as->mcbot = mxp;
97 as->mclim = as->mcbot + MCLIM_REDZONE;
98 return mxp - EXITSTUBS_PER_GROUP;
99 }
100
101 /* Setup all needed exit stubs. */
102 static void asm_exitstub_setup(ASMState *as, ExitNo nexits)
103 {
104 ExitNo i;
105 if (nexits >= EXITSTUBS_PER_GROUP*LJ_MAX_EXITSTUBGR)
106 lj_trace_err(as->J, LJ_TRERR_SNAPOV);
107 for (i = 0; i < (nexits+EXITSTUBS_PER_GROUP-1)/EXITSTUBS_PER_GROUP; i++)
108 if (as->J->exitstubgroup[i] == NULL)
109 as->J->exitstubgroup[i] = asm_exitstub_gen(as, i);
110 }
111
112 /* Emit conditional branch to exit for guard. */
113 static void asm_guardcc(ASMState *as, ARMCC cc)
114 {
115 MCode *target = exitstub_addr(as->J, as->snapno);
116 MCode *p = as->mcp;
117 if (LJ_UNLIKELY(p == as->invmcp)) {
118 as->loopinv = 1;
119 *p = ARMI_BL | ((target-p-2) & 0x00ffffffu);
120 emit_branch(as, ARMF_CC(ARMI_B, cc^1), p+1);
121 return;
122 }
123 emit_branch(as, ARMF_CC(ARMI_BL, cc), target);
124 }
125
126 /* -- Operand fusion ------------------------------------------------------ */
127
128 /* Limit linear search to this distance. Avoids O(n^2) behavior. */
129 #define CONFLICT_SEARCH_LIM 31
130
131 /* Check if there's no conflicting instruction between curins and ref. */
132 static int noconflict(ASMState *as, IRRef ref, IROp conflict)
133 {
134 IRIns *ir = as->ir;
135 IRRef i = as->curins;
136 if (i > ref + CONFLICT_SEARCH_LIM)
137 return 0; /* Give up, ref is too far away. */
138 while (--i > ref)
139 if (ir[i].o == conflict)
140 return 0; /* Conflict found. */
141 return 1; /* Ok, no conflict. */
142 }
143
144 /* Fuse the array base of colocated arrays. */
145 static int32_t asm_fuseabase(ASMState *as, IRRef ref)
146 {
147 IRIns *ir = IR(ref);
148 if (ir->o == IR_TNEW && ir->op1 <= LJ_MAX_COLOSIZE &&
149 !neverfuse(as) && noconflict(as, ref, IR_NEWREF))
150 return (int32_t)sizeof(GCtab);
151 return 0;
152 }
153
154 /* Fuse array/hash/upvalue reference into register+offset operand. */
155 static Reg asm_fuseahuref(ASMState *as, IRRef ref, int32_t *ofsp, RegSet allow,
156 int lim)
157 {
158 IRIns *ir = IR(ref);
159 if (ra_noreg(ir->r)) {
160 if (ir->o == IR_AREF) {
161 if (mayfuse(as, ref)) {
162 if (irref_isk(ir->op2)) {
163 IRRef tab = IR(ir->op1)->op1;
164 int32_t ofs = asm_fuseabase(as, tab);
165 IRRef refa = ofs ? tab : ir->op1;
166 ofs += 8*IR(ir->op2)->i;
167 if (ofs > -lim && ofs < lim) {
168 *ofsp = ofs;
169 return ra_alloc1(as, refa, allow);
170 }
171 }
172 }
173 } else if (ir->o == IR_HREFK) {
174 if (mayfuse(as, ref)) {
175 int32_t ofs = (int32_t)(IR(ir->op2)->op2 * sizeof(Node));
176 if (ofs < lim) {
177 *ofsp = ofs;
178 return ra_alloc1(as, ir->op1, allow);
179 }
180 }
181 } else if (ir->o == IR_UREFC) {
182 if (irref_isk(ir->op1)) {
183 GCfunc *fn = ir_kfunc(IR(ir->op1));
184 int32_t ofs = i32ptr(&gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.tv);
185 *ofsp = (ofs & 255); /* Mask out less bits to allow LDRD. */
186 return ra_allock(as, (ofs & ~255), allow);
187 }
188 } else if (ir->o == IR_TMPREF) {
189 *ofsp = 0;
190 return RID_SP;
191 }
192 }
193 *ofsp = 0;
194 return ra_alloc1(as, ref, allow);
195 }
196
197 /* Fuse m operand into arithmetic/logic instructions. */
198 static uint32_t asm_fuseopm(ASMState *as, ARMIns ai, IRRef ref, RegSet allow)
199 {
200 IRIns *ir = IR(ref);
201 if (ra_hasreg(ir->r)) {
202 ra_noweak(as, ir->r);
203 return ARMF_M(ir->r);
204 } else if (irref_isk(ref)) {
205 uint32_t k = emit_isk12(ai, ir->i);
206 if (k)
207 return k;
208 } else if (mayfuse(as, ref)) {
209 if (ir->o >= IR_BSHL && ir->o <= IR_BROR) {
210 Reg m = ra_alloc1(as, ir->op1, allow);
211 ARMShift sh = ir->o == IR_BSHL ? ARMSH_LSL :
212 ir->o == IR_BSHR ? ARMSH_LSR :
213 ir->o == IR_BSAR ? ARMSH_ASR : ARMSH_ROR;
214 if (irref_isk(ir->op2)) {
215 return m | ARMF_SH(sh, (IR(ir->op2)->i & 31));
216 } else {
217 Reg s = ra_alloc1(as, ir->op2, rset_exclude(allow, m));
218 return m | ARMF_RSH(sh, s);
219 }
220 } else if (ir->o == IR_ADD && ir->op1 == ir->op2) {
221 Reg m = ra_alloc1(as, ir->op1, allow);
222 return m | ARMF_SH(ARMSH_LSL, 1);
223 }
224 }
225 return ra_allocref(as, ref, allow);
226 }
227
228 /* Fuse shifts into loads/stores. Only bother with BSHL 2 => lsl #2. */
229 static IRRef asm_fuselsl2(ASMState *as, IRRef ref)
230 {
231 IRIns *ir = IR(ref);
232 if (ra_noreg(ir->r) && mayfuse(as, ref) && ir->o == IR_BSHL &&
233 irref_isk(ir->op2) && IR(ir->op2)->i == 2)
234 return ir->op1;
235 return 0; /* No fusion. */
236 }
237
238 /* Fuse XLOAD/XSTORE reference into load/store operand. */
239 static void asm_fusexref(ASMState *as, ARMIns ai, Reg rd, IRRef ref,
240 RegSet allow, int32_t ofs)
241 {
242 IRIns *ir = IR(ref);
243 Reg base;
244 if (ra_noreg(ir->r) && canfuse(as, ir)) {
245 int32_t lim = (!LJ_SOFTFP && (ai & 0x08000000)) ? 1024 :
246 (ai & 0x04000000) ? 4096 : 256;
247 if (ir->o == IR_ADD) {
248 int32_t ofs2;
249 if (irref_isk(ir->op2) &&
250 (ofs2 = ofs + IR(ir->op2)->i) > -lim && ofs2 < lim &&
251 (!(!LJ_SOFTFP && (ai & 0x08000000)) || !(ofs2 & 3))) {
252 ofs = ofs2;
253 ref = ir->op1;
254 } else if (ofs == 0 && !(!LJ_SOFTFP && (ai & 0x08000000))) {
255 IRRef lref = ir->op1, rref = ir->op2;
256 Reg rn, rm;
257 if ((ai & 0x04000000)) {
258 IRRef sref = asm_fuselsl2(as, rref);
259 if (sref) {
260 rref = sref;
261 ai |= ARMF_SH(ARMSH_LSL, 2);
262 } else if ((sref = asm_fuselsl2(as, lref)) != 0) {
263 lref = rref;
264 rref = sref;
265 ai |= ARMF_SH(ARMSH_LSL, 2);
266 }
267 }
268 rn = ra_alloc1(as, lref, allow);
269 rm = ra_alloc1(as, rref, rset_exclude(allow, rn));
270 if ((ai & 0x04000000)) ai |= ARMI_LS_R;
271 emit_dnm(as, ai|ARMI_LS_P|ARMI_LS_U, rd, rn, rm);
272 return;
273 }
274 } else if (ir->o == IR_STRREF && !(!LJ_SOFTFP && (ai & 0x08000000))) {
275 lj_assertA(ofs == 0, "bad usage");
276 ofs = (int32_t)sizeof(GCstr);
277 if (irref_isk(ir->op2)) {
278 ofs += IR(ir->op2)->i;
279 ref = ir->op1;
280 } else if (irref_isk(ir->op1)) {
281 ofs += IR(ir->op1)->i;
282 ref = ir->op2;
283 } else {
284 /* NYI: Fuse ADD with constant. */
285 Reg rn = ra_alloc1(as, ir->op1, allow);
286 uint32_t m = asm_fuseopm(as, 0, ir->op2, rset_exclude(allow, rn));
287 if ((ai & 0x04000000))
288 emit_lso(as, ai, rd, rd, ofs);
289 else
290 emit_lsox(as, ai, rd, rd, ofs);
291 emit_dn(as, ARMI_ADD^m, rd, rn);
292 return;
293 }
294 if (ofs <= -lim || ofs >= lim) {
295 Reg rn = ra_alloc1(as, ref, allow);
296 Reg rm = ra_allock(as, ofs, rset_exclude(allow, rn));
297 if ((ai & 0x04000000)) ai |= ARMI_LS_R;
298 emit_dnm(as, ai|ARMI_LS_P|ARMI_LS_U, rd, rn, rm);
299 return;
300 }
301 }
302 }
303 base = ra_alloc1(as, ref, allow);
304 #if !LJ_SOFTFP
305 if ((ai & 0x08000000))
306 emit_vlso(as, ai, rd, base, ofs);
307 else
308 #endif
309 if ((ai & 0x04000000))
310 emit_lso(as, ai, rd, base, ofs);
311 else
312 emit_lsox(as, ai, rd, base, ofs);
313 }
314
315 #if !LJ_SOFTFP
316 /*
317 ** Fuse to multiply-add/sub instruction.
318 ** VMLA rounds twice (UMA, not FMA) -- no need to check for JIT_F_OPT_FMA.
319 ** VFMA needs VFPv4, which is uncommon on the remaining ARM32 targets.
320 */
321 static int asm_fusemadd(ASMState *as, IRIns *ir, ARMIns ai, ARMIns air)
322 {
323 IRRef lref = ir->op1, rref = ir->op2;
324 IRIns *irm;
325 if (lref != rref &&
326 ((mayfuse(as, lref) && (irm = IR(lref), irm->o == IR_MUL) &&
327 ra_noreg(irm->r)) ||
328 (mayfuse(as, rref) && (irm = IR(rref), irm->o == IR_MUL) &&
329 (rref = lref, ai = air, ra_noreg(irm->r))))) {
330 Reg dest = ra_dest(as, ir, RSET_FPR);
331 Reg add = ra_hintalloc(as, rref, dest, RSET_FPR);
332 Reg right, left = ra_alloc2(as, irm,
333 rset_exclude(rset_exclude(RSET_FPR, dest), add));
334 right = (left >> 8); left &= 255;
335 emit_dnm(as, ai, (dest & 15), (left & 15), (right & 15));
336 if (dest != add) emit_dm(as, ARMI_VMOV_D, (dest & 15), (add & 15));
337 return 1;
338 }
339 return 0;
340 }
341 #endif
342
343 /* -- Calls --------------------------------------------------------------- */
344
345 /* Generate a call to a C function. */
346 static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
347 {
348 uint32_t n, nargs = CCI_XNARGS(ci);
349 int32_t ofs = 0;
350 #if LJ_SOFTFP
351 Reg gpr = REGARG_FIRSTGPR;
352 #else
353 Reg gpr, fpr = REGARG_FIRSTFPR, fprodd = 0;
354 #endif
355 if ((void *)ci->func)
356 emit_call(as, (void *)ci->func);
357 #if !LJ_SOFTFP
358 for (gpr = REGARG_FIRSTGPR; gpr <= REGARG_LASTGPR; gpr++)
359 as->cost[gpr] = REGCOST(~0u, ASMREF_L);
360 gpr = REGARG_FIRSTGPR;
361 #endif
362 for (n = 0; n < nargs; n++) { /* Setup args. */
363 IRRef ref = args[n];
364 IRIns *ir = IR(ref);
365 #if !LJ_SOFTFP
366 if (ref && irt_isfp(ir->t)) {
367 RegSet of = as->freeset;
368 Reg src;
369 if (!LJ_ABI_SOFTFP && !(ci->flags & CCI_VARARG)) {
370 if (irt_isnum(ir->t)) {
371 if (fpr <= REGARG_LASTFPR) {
372 ra_leftov(as, fpr, ref);
373 fpr++;
374 continue;
375 }
376 } else if (fprodd) { /* Ick. */
377 src = ra_alloc1(as, ref, RSET_FPR);
378 emit_dm(as, ARMI_VMOV_S, (fprodd & 15), (src & 15) | 0x00400000);
379 fprodd = 0;
380 continue;
381 } else if (fpr <= REGARG_LASTFPR) {
382 ra_leftov(as, fpr, ref);
383 fprodd = fpr++;
384 continue;
385 }
386 /* Workaround to protect argument GPRs from being used for remat. */
387 as->freeset &= ~RSET_RANGE(REGARG_FIRSTGPR, REGARG_LASTGPR+1);
388 src = ra_alloc1(as, ref, RSET_FPR); /* May alloc GPR to remat FPR. */
389 as->freeset |= (of & RSET_RANGE(REGARG_FIRSTGPR, REGARG_LASTGPR+1));
390 fprodd = 0;
391 goto stackfp;
392 }
393 /* Workaround to protect argument GPRs from being used for remat. */
394 as->freeset &= ~RSET_RANGE(REGARG_FIRSTGPR, REGARG_LASTGPR+1);
395 src = ra_alloc1(as, ref, RSET_FPR); /* May alloc GPR to remat FPR. */
396 as->freeset |= (of & RSET_RANGE(REGARG_FIRSTGPR, REGARG_LASTGPR+1));
397 if (irt_isnum(ir->t)) gpr = (gpr+1) & ~1u;
398 if (gpr <= REGARG_LASTGPR) {
399 lj_assertA(rset_test(as->freeset, gpr),
400 "reg %d not free", gpr); /* Must have been evicted. */
401 if (irt_isnum(ir->t)) {
402 lj_assertA(rset_test(as->freeset, gpr+1),
403 "reg %d not free", gpr+1); /* Ditto. */
404 emit_dnm(as, ARMI_VMOV_RR_D, gpr, gpr+1, (src & 15));
405 gpr += 2;
406 } else {
407 emit_dn(as, ARMI_VMOV_R_S, gpr, (src & 15));
408 gpr++;
409 }
410 } else {
411 stackfp:
412 if (irt_isnum(ir->t)) ofs = (ofs + 4) & ~4;
413 emit_spstore(as, ir, src, ofs);
414 ofs += irt_isnum(ir->t) ? 8 : 4;
415 }
416 } else
417 #endif
418 {
419 if (gpr <= REGARG_LASTGPR) {
420 lj_assertA(rset_test(as->freeset, gpr),
421 "reg %d not free", gpr); /* Must have been evicted. */
422 if (ref) ra_leftov(as, gpr, ref);
423 gpr++;
424 } else {
425 if (ref) {
426 Reg r = ra_alloc1(as, ref, RSET_GPR);
427 emit_spstore(as, ir, r, ofs);
428 }
429 ofs += 4;
430 }
431 }
432 }
433 }
434
435 /* Setup result reg/sp for call. Evict scratch regs. */
436 static void asm_setupresult(ASMState *as, IRIns *ir, const CCallInfo *ci)
437 {
438 RegSet drop = RSET_SCRATCH;
439 int hiop = ((ir+1)->o == IR_HIOP && !irt_isnil((ir+1)->t));
440 if (ra_hasreg(ir->r))
441 rset_clear(drop, ir->r); /* Dest reg handled below. */
442 if (hiop && ra_hasreg((ir+1)->r))
443 rset_clear(drop, (ir+1)->r); /* Dest reg handled below. */
444 ra_evictset(as, drop); /* Evictions must be performed first. */
445 if (ra_used(ir)) {
446 lj_assertA(!irt_ispri(ir->t), "PRI dest");
447 if (!LJ_SOFTFP && irt_isfp(ir->t)) {
448 if (LJ_ABI_SOFTFP || (ci->flags & (CCI_CASTU64|CCI_VARARG))) {
449 Reg dest = (ra_dest(as, ir, RSET_FPR) & 15);
450 if (irt_isnum(ir->t))
451 emit_dnm(as, ARMI_VMOV_D_RR, RID_RETLO, RID_RETHI, dest);
452 else
453 emit_dn(as, ARMI_VMOV_S_R, RID_RET, dest);
454 } else {
455 ra_destreg(as, ir, RID_FPRET);
456 }
457 } else if (hiop) {
458 ra_destpair(as, ir);
459 } else {
460 ra_destreg(as, ir, RID_RET);
461 }
462 }
463 UNUSED(ci);
464 }
465
466 static void asm_callx(ASMState *as, IRIns *ir)
467 {
468 IRRef args[CCI_NARGS_MAX*2];
469 CCallInfo ci;
470 IRRef func;
471 IRIns *irf;
472 ci.flags = asm_callx_flags(as, ir);
473 asm_collectargs(as, ir, &ci, args);
474 asm_setupresult(as, ir, &ci);
475 func = ir->op2; irf = IR(func);
476 if (irf->o == IR_CARG) { func = irf->op1; irf = IR(func); }
477 if (irref_isk(func)) { /* Call to constant address. */
478 ci.func = (ASMFunction)(void *)(irf->i);
479 } else { /* Need a non-argument register for indirect calls. */
480 Reg freg = ra_alloc1(as, func, RSET_RANGE(RID_R4, RID_R12+1));
481 emit_m(as, ARMI_BLXr, freg);
482 ci.func = (ASMFunction)(void *)0;
483 }
484 asm_gencall(as, &ci, args);
485 }
486
487 /* -- Returns ------------------------------------------------------------- */
488
489 /* Return to lower frame. Guard that it goes to the right spot. */
490 static void asm_retf(ASMState *as, IRIns *ir)
491 {
492 Reg base = ra_alloc1(as, REF_BASE, RSET_GPR);
493 void *pc = ir_kptr(IR(ir->op2));
494 int32_t delta = 1+LJ_FR2+bc_a(*((const BCIns *)pc - 1));
495 as->topslot -= (BCReg)delta;
496 if ((int32_t)as->topslot < 0) as->topslot = 0;
497 irt_setmark(IR(REF_BASE)->t); /* Children must not coalesce with BASE reg. */
498 /* Need to force a spill on REF_BASE now to update the stack slot. */
499 emit_lso(as, ARMI_STR, base, RID_SP, ra_spill(as, IR(REF_BASE)));
500 emit_setgl(as, base, jit_base);
501 emit_addptr(as, base, -8*delta);
502 asm_guardcc(as, CC_NE);
503 emit_nm(as, ARMI_CMP, RID_TMP,
504 ra_allock(as, i32ptr(pc), rset_exclude(RSET_GPR, base)));
505 emit_lso(as, ARMI_LDR, RID_TMP, base, -4);
506 }
507
508 /* -- Buffer operations --------------------------------------------------- */
509
510 #if LJ_HASBUFFER
511 static void asm_bufhdr_write(ASMState *as, Reg sb)
512 {
513 Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, sb));
514 IRIns irgc;
515 int32_t addr = i32ptr((void *)&J2G(as->J)->cur_L);
516 irgc.ot = IRT(0, IRT_PGC); /* GC type. */
517 emit_storeofs(as, &irgc, RID_TMP, sb, offsetof(SBuf, L));
518 if ((as->flags & JIT_F_ARMV6T2)) {
519 emit_dnm(as, ARMI_BFI, RID_TMP, lj_fls(SBUF_MASK_FLAG), tmp);
520 } else {
521 emit_dnm(as, ARMI_ORR, RID_TMP, RID_TMP, tmp);
522 emit_dn(as, ARMI_AND|ARMI_K12|SBUF_MASK_FLAG, tmp, tmp);
523 }
524 emit_lso(as, ARMI_LDR, RID_TMP,
525 ra_allock(as, (addr & ~4095),
526 rset_exclude(rset_exclude(RSET_GPR, sb), tmp)),
527 (addr & 4095));
528 emit_loadofs(as, &irgc, tmp, sb, offsetof(SBuf, L));
529 }
530 #endif
531
532 /* -- Type conversions ---------------------------------------------------- */
533
534 #if !LJ_SOFTFP
535 static void asm_tointg(ASMState *as, IRIns *ir, Reg left)
536 {
537 Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
538 Reg dest = ra_dest(as, ir, RSET_GPR);
539 asm_guardcc(as, CC_NE);
540 emit_d(as, ARMI_VMRS, 0);
541 emit_dm(as, ARMI_VCMP_D, (tmp & 15), (left & 15));
542 emit_dm(as, ARMI_VCVT_F64_S32, (tmp & 15), (tmp & 15));
543 emit_dn(as, ARMI_VMOV_R_S, dest, (tmp & 15));
544 emit_dm(as, ARMI_VCVT_S32_F64, (tmp & 15), (left & 15));
545 }
546
547 static void asm_tobit(ASMState *as, IRIns *ir)
548 {
549 RegSet allow = RSET_FPR;
550 Reg left = ra_alloc1(as, ir->op1, allow);
551 Reg right = ra_alloc1(as, ir->op2, rset_clear(allow, left));
552 Reg tmp = ra_scratch(as, rset_clear(allow, right));
553 Reg dest = ra_dest(as, ir, RSET_GPR);
554 emit_dn(as, ARMI_VMOV_R_S, dest, (tmp & 15));
555 emit_dnm(as, ARMI_VADD_D, (tmp & 15), (left & 15), (right & 15));
556 }
557 #endif
558
559 static void asm_conv(ASMState *as, IRIns *ir)
560 {
561 IRType st = (IRType)(ir->op2 & IRCONV_SRCMASK);
562 #if !LJ_SOFTFP
563 int stfp = (st == IRT_NUM || st == IRT_FLOAT);
564 #endif
565 IRRef lref = ir->op1;
566 /* 64 bit integer conversions are handled by SPLIT. */
567 lj_assertA(!irt_isint64(ir->t) && !(st == IRT_I64 || st == IRT_U64),
568 "IR %04d has unsplit 64 bit type",
569 (int)(ir - as->ir) - REF_BIAS);
570 #if LJ_SOFTFP
571 /* FP conversions are handled by SPLIT. */
572 lj_assertA(!irt_isfp(ir->t) && !(st == IRT_NUM || st == IRT_FLOAT),
573 "IR %04d has FP type",
574 (int)(ir - as->ir) - REF_BIAS);
575 /* Can't check for same types: SPLIT uses CONV int.int + BXOR for sfp NEG. */
576 #else
577 lj_assertA(irt_type(ir->t) != st, "inconsistent types for CONV");
578 if (irt_isfp(ir->t)) {
579 Reg dest = ra_dest(as, ir, RSET_FPR);
580 if (stfp) { /* FP to FP conversion. */
581 emit_dm(as, st == IRT_NUM ? ARMI_VCVT_F32_F64 : ARMI_VCVT_F64_F32,
582 (dest & 15), (ra_alloc1(as, lref, RSET_FPR) & 15));
583 } else { /* Integer to FP conversion. */
584 Reg left = ra_alloc1(as, lref, RSET_GPR);
585 ARMIns ai = irt_isfloat(ir->t) ?
586 (st == IRT_INT ? ARMI_VCVT_F32_S32 : ARMI_VCVT_F32_U32) :
587 (st == IRT_INT ? ARMI_VCVT_F64_S32 : ARMI_VCVT_F64_U32);
588 emit_dm(as, ai, (dest & 15), (dest & 15));
589 emit_dn(as, ARMI_VMOV_S_R, left, (dest & 15));
590 }
591 } else if (stfp) { /* FP to integer conversion. */
592 if (irt_isguard(ir->t)) {
593 /* Checked conversions are only supported from number to int. */
594 lj_assertA(irt_isint(ir->t) && st == IRT_NUM,
595 "bad type for checked CONV");
596 asm_tointg(as, ir, ra_alloc1(as, lref, RSET_FPR));
597 } else {
598 Reg left = ra_alloc1(as, lref, RSET_FPR);
599 Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
600 Reg dest = ra_dest(as, ir, RSET_GPR);
601 ARMIns ai;
602 emit_dn(as, ARMI_VMOV_R_S, dest, (tmp & 15));
603 ai = irt_isint(ir->t) ?
604 (st == IRT_NUM ? ARMI_VCVT_S32_F64 : ARMI_VCVT_S32_F32) :
605 (st == IRT_NUM ? ARMI_VCVT_U32_F64 : ARMI_VCVT_U32_F32);
606 emit_dm(as, ai, (tmp & 15), (left & 15));
607 }
608 } else
609 #endif
610 {
611 Reg dest = ra_dest(as, ir, RSET_GPR);
612 if (st >= IRT_I8 && st <= IRT_U16) { /* Extend to 32 bit integer. */
613 Reg left = ra_alloc1(as, lref, RSET_GPR);
614 lj_assertA(irt_isint(ir->t) || irt_isu32(ir->t), "bad type for CONV EXT");
615 if ((as->flags & JIT_F_ARMV6)) {
616 ARMIns ai = st == IRT_I8 ? ARMI_SXTB :
617 st == IRT_U8 ? ARMI_UXTB :
618 st == IRT_I16 ? ARMI_SXTH : ARMI_UXTH;
619 emit_dm(as, ai, dest, left);
620 } else if (st == IRT_U8) {
621 emit_dn(as, ARMI_AND|ARMI_K12|255, dest, left);
622 } else {
623 uint32_t shift = st == IRT_I8 ? 24 : 16;
624 ARMShift sh = st == IRT_U16 ? ARMSH_LSR : ARMSH_ASR;
625 emit_dm(as, ARMI_MOV|ARMF_SH(sh, shift), dest, RID_TMP);
626 emit_dm(as, ARMI_MOV|ARMF_SH(ARMSH_LSL, shift), RID_TMP, left);
627 }
628 } else { /* Handle 32/32 bit no-op (cast). */
629 ra_leftov(as, dest, lref); /* Do nothing, but may need to move regs. */
630 }
631 }
632 }
633
634 static void asm_strto(ASMState *as, IRIns *ir)
635 {
636 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_strscan_num];
637 IRRef args[2];
638 Reg rlo = 0, rhi = 0, tmp;
639 int destused = ra_used(ir);
640 int32_t ofs = 0;
641 ra_evictset(as, RSET_SCRATCH);
642 #if LJ_SOFTFP
643 if (destused) {
644 if (ra_hasspill(ir->s) && ra_hasspill((ir+1)->s) &&
645 (ir->s & 1) == 0 && ir->s + 1 == (ir+1)->s) {
646 int i;
647 for (i = 0; i < 2; i++) {
648 Reg r = (ir+i)->r;
649 if (ra_hasreg(r)) {
650 ra_free(as, r);
651 ra_modified(as, r);
652 emit_spload(as, ir+i, r, sps_scale((ir+i)->s));
653 }
654 }
655 ofs = sps_scale(ir->s);
656 destused = 0;
657 } else {
658 rhi = ra_dest(as, ir+1, RSET_GPR);
659 rlo = ra_dest(as, ir, rset_exclude(RSET_GPR, rhi));
660 }
661 }
662 asm_guardcc(as, CC_EQ);
663 if (destused) {
664 emit_lso(as, ARMI_LDR, rhi, RID_SP, 4);
665 emit_lso(as, ARMI_LDR, rlo, RID_SP, 0);
666 }
667 #else
668 UNUSED(rhi);
669 if (destused) {
670 if (ra_hasspill(ir->s)) {
671 ofs = sps_scale(ir->s);
672 destused = 0;
673 if (ra_hasreg(ir->r)) {
674 ra_free(as, ir->r);
675 ra_modified(as, ir->r);
676 emit_spload(as, ir, ir->r, ofs);
677 }
678 } else {
679 rlo = ra_dest(as, ir, RSET_FPR);
680 }
681 }
682 asm_guardcc(as, CC_EQ);
683 if (destused)
684 emit_vlso(as, ARMI_VLDR_D, rlo, RID_SP, 0);
685 #endif
686 emit_n(as, ARMI_CMP|ARMI_K12|0, RID_RET); /* Test return status. */
687 args[0] = ir->op1; /* GCstr *str */
688 args[1] = ASMREF_TMP1; /* TValue *n */
689 asm_gencall(as, ci, args);
690 tmp = ra_releasetmp(as, ASMREF_TMP1);
691 if (ofs == 0)
692 emit_dm(as, ARMI_MOV, tmp, RID_SP);
693 else
694 emit_opk(as, ARMI_ADD, tmp, RID_SP, ofs, RSET_GPR);
695 }
696
697 /* -- Memory references --------------------------------------------------- */
698
699 /* Get pointer to TValue. */
700 static void asm_tvptr(ASMState *as, Reg dest, IRRef ref, MSize mode)
701 {
702 if ((mode & IRTMPREF_IN1)) {
703 IRIns *ir = IR(ref);
704 if (irt_isnum(ir->t)) {
705 if ((mode & IRTMPREF_OUT1)) {
706 #if LJ_SOFTFP
707 lj_assertA(irref_isk(ref), "unsplit FP op");
708 emit_dm(as, ARMI_MOV, dest, RID_SP);
709 emit_lso(as, ARMI_STR,
710 ra_allock(as, (int32_t)ir_knum(ir)->u32.lo, RSET_GPR),
711 RID_SP, 0);
712 emit_lso(as, ARMI_STR,
713 ra_allock(as, (int32_t)ir_knum(ir)->u32.hi, RSET_GPR),
714 RID_SP, 4);
715 #else
716 Reg src = ra_alloc1(as, ref, RSET_FPR);
717 emit_dm(as, ARMI_MOV, dest, RID_SP);
718 emit_vlso(as, ARMI_VSTR_D, src, RID_SP, 0);
719 #endif
720 } else if (irref_isk(ref)) {
721 /* Use the number constant itself as a TValue. */
722 ra_allockreg(as, i32ptr(ir_knum(ir)), dest);
723 } else {
724 #if LJ_SOFTFP
725 lj_assertA(0, "unsplit FP op");
726 #else
727 /* Otherwise force a spill and use the spill slot. */
728 emit_opk(as, ARMI_ADD, dest, RID_SP, ra_spill(as, ir), RSET_GPR);
729 #endif
730 }
731 } else {
732 /* Otherwise use [sp] and [sp+4] to hold the TValue.
733 ** This assumes the following call has max. 4 args.
734 */
735 Reg type;
736 emit_dm(as, ARMI_MOV, dest, RID_SP);
737 if (!irt_ispri(ir->t)) {
738 Reg src = ra_alloc1(as, ref, RSET_GPR);
739 emit_lso(as, ARMI_STR, src, RID_SP, 0);
740 }
741 if (LJ_SOFTFP && (ir+1)->o == IR_HIOP && !irt_isnil((ir+1)->t))
742 type = ra_alloc1(as, ref+1, RSET_GPR);
743 else
744 type = ra_allock(as, irt_toitype(ir->t), RSET_GPR);
745 emit_lso(as, ARMI_STR, type, RID_SP, 4);
746 }
747 } else {
748 emit_dm(as, ARMI_MOV, dest, RID_SP);
749 }
750 }
751
752 static void asm_aref(ASMState *as, IRIns *ir)
753 {
754 Reg dest = ra_dest(as, ir, RSET_GPR);
755 Reg idx, base;
756 if (irref_isk(ir->op2)) {
757 IRRef tab = IR(ir->op1)->op1;
758 int32_t ofs = asm_fuseabase(as, tab);
759 IRRef refa = ofs ? tab : ir->op1;
760 uint32_t k = emit_isk12(ARMI_ADD, ofs + 8*IR(ir->op2)->i);
761 if (k) {
762 base = ra_alloc1(as, refa, RSET_GPR);
763 emit_dn(as, ARMI_ADD^k, dest, base);
764 return;
765 }
766 }
767 base = ra_alloc1(as, ir->op1, RSET_GPR);
768 idx = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, base));
769 emit_dnm(as, ARMI_ADD|ARMF_SH(ARMSH_LSL, 3), dest, base, idx);
770 }
771
772 /* Inlined hash lookup. Specialized for key type and for const keys.
773 ** The equivalent C code is:
774 ** Node *n = hashkey(t, key);
775 ** do {
776 ** if (lj_obj_equal(&n->key, key)) return &n->val;
777 ** } while ((n = nextnode(n)));
778 ** return niltv(L);
779 */
780 static void asm_href(ASMState *as, IRIns *ir, IROp merge)
781 {
782 RegSet allow = RSET_GPR;
783 int destused = ra_used(ir);
784 Reg dest = ra_dest(as, ir, allow);
785 Reg tab = ra_alloc1(as, ir->op1, rset_clear(allow, dest));
786 Reg key = 0, keyhi = 0, keynumhi = RID_NONE, tmp = RID_TMP;
787 IRRef refkey = ir->op2;
788 IRIns *irkey = IR(refkey);
789 IRType1 kt = irkey->t;
790 int32_t k = 0, khi = emit_isk12(ARMI_CMP, irt_toitype(kt));
791 uint32_t khash;
792 MCLabel l_end, l_loop;
793 rset_clear(allow, tab);
794 if (!irref_isk(refkey) || irt_isstr(kt)) {
795 #if LJ_SOFTFP
796 key = ra_alloc1(as, refkey, allow);
797 rset_clear(allow, key);
798 if (irkey[1].o == IR_HIOP) {
799 if (ra_hasreg((irkey+1)->r)) {
800 keynumhi = (irkey+1)->r;
801 keyhi = RID_TMP;
802 ra_noweak(as, keynumhi);
803 } else {
804 keyhi = keynumhi = ra_allocref(as, refkey+1, allow);
805 }
806 rset_clear(allow, keynumhi);
807 khi = 0;
808 }
809 #else
810 if (irt_isnum(kt)) {
811 key = ra_scratch(as, allow);
812 rset_clear(allow, key);
813 keyhi = keynumhi = ra_scratch(as, allow);
814 rset_clear(allow, keyhi);
815 khi = 0;
816 } else {
817 key = ra_alloc1(as, refkey, allow);
818 rset_clear(allow, key);
819 }
820 #endif
821 } else if (irt_isnum(kt)) {
822 int32_t val = (int32_t)ir_knum(irkey)->u32.lo;
823 k = emit_isk12(ARMI_CMP, val);
824 if (!k) {
825 key = ra_allock(as, val, allow);
826 rset_clear(allow, key);
827 }
828 val = (int32_t)ir_knum(irkey)->u32.hi;
829 khi = emit_isk12(ARMI_CMP, val);
830 if (!khi) {
831 keyhi = ra_allock(as, val, allow);
832 rset_clear(allow, keyhi);
833 }
834 } else if (!irt_ispri(kt)) {
835 k = emit_isk12(ARMI_CMP, irkey->i);
836 if (!k) {
837 key = ra_alloc1(as, refkey, allow);
838 rset_clear(allow, key);
839 }
840 }
841 if (!irt_ispri(kt))
842 tmp = ra_scratchpair(as, allow);
843
844 /* Key not found in chain: jump to exit (if merged) or load niltv. */
845 l_end = emit_label(as);
846 as->invmcp = NULL;
847 if (merge == IR_NE)
848 asm_guardcc(as, CC_AL);
849 else if (destused)
850 emit_loada(as, dest, niltvg(J2G(as->J)));
851
852 /* Follow hash chain until the end. */
853 l_loop = --as->mcp;
854 emit_n(as, ARMI_CMP|ARMI_K12|0, dest);
855 emit_lso(as, ARMI_LDR, dest, dest, (int32_t)offsetof(Node, next));
856
857 /* Type and value comparison. */
858 if (merge == IR_EQ)
859 asm_guardcc(as, CC_EQ);
860 else
861 emit_branch(as, ARMF_CC(ARMI_B, CC_EQ), l_end);
862 if (!irt_ispri(kt)) {
863 emit_nm(as, ARMF_CC(ARMI_CMP, CC_EQ)^k, tmp, key);
864 emit_nm(as, ARMI_CMP^khi, tmp+1, keyhi);
865 emit_lsox(as, ARMI_LDRD, tmp, dest, (int32_t)offsetof(Node, key));
866 } else {
867 emit_n(as, ARMI_CMP^khi, tmp);
868 emit_lso(as, ARMI_LDR, tmp, dest, (int32_t)offsetof(Node, key.it));
869 }
870 *l_loop = ARMF_CC(ARMI_B, CC_NE) | ((as->mcp-l_loop-2) & 0x00ffffffu);
871
872 /* Load main position relative to tab->node into dest. */
873 khash = irref_isk(refkey) ? ir_khash(as, irkey) : 1;
874 if (khash == 0) {
875 emit_lso(as, ARMI_LDR, dest, tab, (int32_t)offsetof(GCtab, node));
876 } else {
877 emit_dnm(as, ARMI_ADD|ARMF_SH(ARMSH_LSL, 3), dest, dest, tmp);
878 emit_dnm(as, ARMI_ADD|ARMF_SH(ARMSH_LSL, 1), tmp, tmp, tmp);
879 if (irt_isstr(kt)) { /* Fetch of str->sid is cheaper than ra_allock. */
880 emit_dnm(as, ARMI_AND, tmp, tmp+1, RID_TMP);
881 emit_lso(as, ARMI_LDR, dest, tab, (int32_t)offsetof(GCtab, node));
882 emit_lso(as, ARMI_LDR, tmp+1, key, (int32_t)offsetof(GCstr, sid));
883 emit_lso(as, ARMI_LDR, RID_TMP, tab, (int32_t)offsetof(GCtab, hmask));
884 } else if (irref_isk(refkey)) {
885 emit_opk(as, ARMI_AND, tmp, RID_TMP, (int32_t)khash,
886 rset_exclude(rset_exclude(RSET_GPR, tab), dest));
887 emit_lso(as, ARMI_LDR, dest, tab, (int32_t)offsetof(GCtab, node));
888 emit_lso(as, ARMI_LDR, RID_TMP, tab, (int32_t)offsetof(GCtab, hmask));
889 } else { /* Must match with hash*() in lj_tab.c. */
890 if (ra_hasreg(keynumhi)) { /* Canonicalize +-0.0 to 0.0. */
891 if (keyhi == RID_TMP)
892 emit_dm(as, ARMF_CC(ARMI_MOV, CC_NE), keyhi, keynumhi);
893 emit_d(as, ARMF_CC(ARMI_MOV, CC_EQ)|ARMI_K12|0, keyhi);
894 }
895 emit_dnm(as, ARMI_AND, tmp, tmp, RID_TMP);
896 emit_dnm(as, ARMI_SUB|ARMF_SH(ARMSH_ROR, 32-HASH_ROT3), tmp, tmp, tmp+1);
897 emit_lso(as, ARMI_LDR, dest, tab, (int32_t)offsetof(GCtab, node));
898 emit_dnm(as, ARMI_EOR|ARMF_SH(ARMSH_ROR, 32-((HASH_ROT2+HASH_ROT1)&31)),
899 tmp, tmp+1, tmp);
900 emit_lso(as, ARMI_LDR, RID_TMP, tab, (int32_t)offsetof(GCtab, hmask));
901 emit_dnm(as, ARMI_SUB|ARMF_SH(ARMSH_ROR, 32-HASH_ROT1), tmp+1, tmp+1, tmp);
902 if (ra_hasreg(keynumhi)) {
903 emit_dnm(as, ARMI_EOR, tmp+1, tmp, key);
904 emit_dnm(as, ARMI_ORR|ARMI_S, RID_TMP, tmp, key); /* Test for +-0.0. */
905 emit_dnm(as, ARMI_ADD, tmp, keynumhi, keynumhi);
906 #if !LJ_SOFTFP
907 emit_dnm(as, ARMI_VMOV_RR_D, key, keynumhi,
908 (ra_alloc1(as, refkey, RSET_FPR) & 15));
909 #endif
910 } else {
911 emit_dnm(as, ARMI_EOR, tmp+1, tmp, key);
912 emit_opk(as, ARMI_ADD, tmp, key, (int32_t)HASH_BIAS,
913 rset_exclude(rset_exclude(RSET_GPR, tab), key));
914 }
915 }
916 }
917 }
918
919 static void asm_hrefk(ASMState *as, IRIns *ir)
920 {
921 IRIns *kslot = IR(ir->op2);
922 IRIns *irkey = IR(kslot->op1);
923 int32_t ofs = (int32_t)(kslot->op2 * sizeof(Node));
924 int32_t kofs = ofs + (int32_t)offsetof(Node, key);
925 Reg dest = (ra_used(ir) || ofs > 4095) ? ra_dest(as, ir, RSET_GPR) : RID_NONE;
926 Reg node = ra_alloc1(as, ir->op1, RSET_GPR);
927 Reg key = RID_NONE, type = RID_TMP, idx = node;
928 RegSet allow = rset_exclude(RSET_GPR, node);
929 lj_assertA(ofs % sizeof(Node) == 0, "unaligned HREFK slot");
930 if (ofs > 4095) {
931 idx = dest;
932 rset_clear(allow, dest);
933 kofs = (int32_t)offsetof(Node, key);
934 } else if (ra_hasreg(dest)) {
935 emit_opk(as, ARMI_ADD, dest, node, ofs, allow);
936 }
937 asm_guardcc(as, CC_NE);
938 if (!irt_ispri(irkey->t)) {
939 RegSet even = (as->freeset & allow);
940 even = even & (even >> 1) & RSET_GPREVEN;
941 if (even) {
942 key = ra_scratch(as, even);
943 if (rset_test(as->freeset, key+1)) {
944 type = key+1;
945 ra_modified(as, type);
946 }
947 } else {
948 key = ra_scratch(as, allow);
949 }
950 rset_clear(allow, key);
951 }
952 rset_clear(allow, type);
953 if (irt_isnum(irkey->t)) {
954 emit_opk(as, ARMF_CC(ARMI_CMP, CC_EQ), 0, type,
955 (int32_t)ir_knum(irkey)->u32.hi, allow);
956 emit_opk(as, ARMI_CMP, 0, key,
957 (int32_t)ir_knum(irkey)->u32.lo, allow);
958 } else {
959 if (ra_hasreg(key))
960 emit_opk(as, ARMF_CC(ARMI_CMP, CC_EQ), 0, key, irkey->i, allow);
961 emit_n(as, ARMI_CMN|ARMI_K12|-irt_toitype(irkey->t), type);
962 }
963 emit_lso(as, ARMI_LDR, type, idx, kofs+4);
964 if (ra_hasreg(key)) emit_lso(as, ARMI_LDR, key, idx, kofs);
965 if (ofs > 4095)
966 emit_opk(as, ARMI_ADD, dest, node, ofs, RSET_GPR);
967 }
968
969 static void asm_uref(ASMState *as, IRIns *ir)
970 {
971 Reg dest = ra_dest(as, ir, RSET_GPR);
972 if (irref_isk(ir->op1)) {
973 GCfunc *fn = ir_kfunc(IR(ir->op1));
974 MRef *v = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.v;
975 emit_lsptr(as, ARMI_LDR, dest, v);
976 } else {
977 Reg uv = ra_scratch(as, RSET_GPR);
978 Reg func = ra_alloc1(as, ir->op1, RSET_GPR);
979 if (ir->o == IR_UREFC) {
980 asm_guardcc(as, CC_NE);
981 emit_n(as, ARMI_CMP|ARMI_K12|1, RID_TMP);
982 emit_opk(as, ARMI_ADD, dest, uv,
983 (int32_t)offsetof(GCupval, tv), RSET_GPR);
984 emit_lso(as, ARMI_LDRB, RID_TMP, uv, (int32_t)offsetof(GCupval, closed));
985 } else {
986 emit_lso(as, ARMI_LDR, dest, uv, (int32_t)offsetof(GCupval, v));
987 }
988 emit_lso(as, ARMI_LDR, uv, func,
989 (int32_t)offsetof(GCfuncL, uvptr) + 4*(int32_t)(ir->op2 >> 8));
990 }
991 }
992
993 static void asm_fref(ASMState *as, IRIns *ir)
994 {
995 UNUSED(as); UNUSED(ir);
996 lj_assertA(!ra_used(ir), "unfused FREF");
997 }
998
999 static void asm_strref(ASMState *as, IRIns *ir)
1000 {
1001 Reg dest = ra_dest(as, ir, RSET_GPR);
1002 IRRef ref = ir->op2, refk = ir->op1;
1003 Reg r;
1004 if (irref_isk(ref)) {
1005 IRRef tmp = refk; refk = ref; ref = tmp;
1006 } else if (!irref_isk(refk)) {
1007 uint32_t k, m = ARMI_K12|sizeof(GCstr);
1008 Reg right, left = ra_alloc1(as, ir->op1, RSET_GPR);
1009 IRIns *irr = IR(ir->op2);
1010 if (ra_hasreg(irr->r)) {
1011 ra_noweak(as, irr->r);
1012 right = irr->r;
1013 } else if (mayfuse(as, irr->op2) &&
1014 irr->o == IR_ADD && irref_isk(irr->op2) &&
1015 (k = emit_isk12(ARMI_ADD,
1016 (int32_t)sizeof(GCstr) + IR(irr->op2)->i))) {
1017 m = k;
1018 right = ra_alloc1(as, irr->op1, rset_exclude(RSET_GPR, left));
1019 } else {
1020 right = ra_allocref(as, ir->op2, rset_exclude(RSET_GPR, left));
1021 }
1022 emit_dn(as, ARMI_ADD^m, dest, dest);
1023 emit_dnm(as, ARMI_ADD, dest, left, right);
1024 return;
1025 }
1026 r = ra_alloc1(as, ref, RSET_GPR);
1027 emit_opk(as, ARMI_ADD, dest, r,
1028 sizeof(GCstr) + IR(refk)->i, rset_exclude(RSET_GPR, r));
1029 }
1030
1031 /* -- Loads and stores ---------------------------------------------------- */
1032
1033 static ARMIns asm_fxloadins(ASMState *as, IRIns *ir)
1034 {
1035 UNUSED(as);
1036 switch (irt_type(ir->t)) {
1037 case IRT_I8: return ARMI_LDRSB;
1038 case IRT_U8: return ARMI_LDRB;
1039 case IRT_I16: return ARMI_LDRSH;
1040 case IRT_U16: return ARMI_LDRH;
1041 case IRT_NUM: lj_assertA(!LJ_SOFTFP, "unsplit FP op"); return ARMI_VLDR_D;
1042 case IRT_FLOAT: if (!LJ_SOFTFP) return ARMI_VLDR_S; /* fallthrough */
1043 default: return ARMI_LDR;
1044 }
1045 }
1046
1047 static ARMIns asm_fxstoreins(ASMState *as, IRIns *ir)
1048 {
1049 UNUSED(as);
1050 switch (irt_type(ir->t)) {
1051 case IRT_I8: case IRT_U8: return ARMI_STRB;
1052 case IRT_I16: case IRT_U16: return ARMI_STRH;
1053 case IRT_NUM: lj_assertA(!LJ_SOFTFP, "unsplit FP op"); return ARMI_VSTR_D;
1054 case IRT_FLOAT: if (!LJ_SOFTFP) return ARMI_VSTR_S; /* fallthrough */
1055 default: return ARMI_STR;
1056 }
1057 }
1058
1059 static void asm_fload(ASMState *as, IRIns *ir)
1060 {
1061 Reg dest = ra_dest(as, ir, RSET_GPR);
1062 ARMIns ai = asm_fxloadins(as, ir);
1063 Reg idx;
1064 int32_t ofs;
1065 if (ir->op1 == REF_NIL) { /* FLOAD from GG_State with offset. */
1066 idx = ra_allock(as, (int32_t)(ir->op2<<2) + (int32_t)J2GG(as->J), RSET_GPR);
1067 ofs = 0;
1068 } else {
1069 idx = ra_alloc1(as, ir->op1, RSET_GPR);
1070 if (ir->op2 == IRFL_TAB_ARRAY) {
1071 ofs = asm_fuseabase(as, ir->op1);
1072 if (ofs) { /* Turn the t->array load into an add for colocated arrays. */
1073 emit_dn(as, ARMI_ADD|ARMI_K12|ofs, dest, idx);
1074 return;
1075 }
1076 }
1077 ofs = field_ofs[ir->op2];
1078 }
1079 if ((ai & 0x04000000))
1080 emit_lso(as, ai, dest, idx, ofs);
1081 else
1082 emit_lsox(as, ai, dest, idx, ofs);
1083 }
1084
1085 static void asm_fstore(ASMState *as, IRIns *ir)
1086 {
1087 if (ir->r != RID_SINK) {
1088 Reg src = ra_alloc1(as, ir->op2, RSET_GPR);
1089 IRIns *irf = IR(ir->op1);
1090 Reg idx = ra_alloc1(as, irf->op1, rset_exclude(RSET_GPR, src));
1091 int32_t ofs = field_ofs[irf->op2];
1092 ARMIns ai = asm_fxstoreins(as, ir);
1093 if ((ai & 0x04000000))
1094 emit_lso(as, ai, src, idx, ofs);
1095 else
1096 emit_lsox(as, ai, src, idx, ofs);
1097 }
1098 }
1099
1100 static void asm_xload(ASMState *as, IRIns *ir)
1101 {
1102 Reg dest = ra_dest(as, ir,
1103 (!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR);
1104 lj_assertA(!(ir->op2 & IRXLOAD_UNALIGNED), "unaligned XLOAD");
1105 asm_fusexref(as, asm_fxloadins(as, ir), dest, ir->op1, RSET_GPR, 0);
1106 }
1107
1108 static void asm_xstore_(ASMState *as, IRIns *ir, int32_t ofs)
1109 {
1110 if (ir->r != RID_SINK) {
1111 Reg src = ra_alloc1(as, ir->op2,
1112 (!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR);
1113 asm_fusexref(as, asm_fxstoreins(as, ir), src, ir->op1,
1114 rset_exclude(RSET_GPR, src), ofs);
1115 }
1116 }
1117
1118 #define asm_xstore(as, ir) asm_xstore_(as, ir, 0)
1119
1120 static void asm_ahuvload(ASMState *as, IRIns *ir)
1121 {
1122 int hiop = (LJ_SOFTFP && (ir+1)->o == IR_HIOP);
1123 IRType t = hiop ? IRT_NUM : irt_type(ir->t);
1124 Reg dest = RID_NONE, type = RID_NONE, idx;
1125 RegSet allow = RSET_GPR;
1126 int32_t ofs = 0;
1127 if (hiop && ra_used(ir+1)) {
1128 type = ra_dest(as, ir+1, allow);
1129 rset_clear(allow, type);
1130 }
1131 if (ra_used(ir)) {
1132 lj_assertA((LJ_SOFTFP ? 0 : irt_isnum(ir->t)) ||
1133 irt_isint(ir->t) || irt_isaddr(ir->t),
1134 "bad load type %d", irt_type(ir->t));
1135 dest = ra_dest(as, ir, (!LJ_SOFTFP && t == IRT_NUM) ? RSET_FPR : allow);
1136 rset_clear(allow, dest);
1137 }
1138 idx = asm_fuseahuref(as, ir->op1, &ofs, allow,
1139 (!LJ_SOFTFP && t == IRT_NUM) ? 1024 : 4096);
1140 if (ir->o == IR_VLOAD) ofs += 8 * ir->op2;
1141 if (!hiop || type == RID_NONE) {
1142 rset_clear(allow, idx);
1143 if (ofs < 256 && ra_hasreg(dest) && (dest & 1) == 0 &&
1144 rset_test((as->freeset & allow), dest+1)) {
1145 type = dest+1;
1146 ra_modified(as, type);
1147 } else {
1148 type = RID_TMP;
1149 }
1150 }
1151 asm_guardcc(as, t == IRT_NUM ? CC_HS : CC_NE);
1152 emit_n(as, ARMI_CMN|ARMI_K12|-irt_toitype_(t), type);
1153 if (ra_hasreg(dest)) {
1154 #if !LJ_SOFTFP
1155 if (t == IRT_NUM)
1156 emit_vlso(as, ARMI_VLDR_D, dest, idx, ofs);
1157 else
1158 #endif
1159 emit_lso(as, ARMI_LDR, dest, idx, ofs);
1160 }
1161 emit_lso(as, ARMI_LDR, type, idx, ofs+4);
1162 }
1163
1164 static void asm_ahustore(ASMState *as, IRIns *ir)
1165 {
1166 if (ir->r != RID_SINK) {
1167 RegSet allow = RSET_GPR;
1168 Reg idx, src = RID_NONE, type = RID_NONE;
1169 int32_t ofs = 0;
1170 #if !LJ_SOFTFP
1171 if (irt_isnum(ir->t)) {
1172 src = ra_alloc1(as, ir->op2, RSET_FPR);
1173 idx = asm_fuseahuref(as, ir->op1, &ofs, allow, 1024);
1174 emit_vlso(as, ARMI_VSTR_D, src, idx, ofs);
1175 } else
1176 #endif
1177 {
1178 int hiop = (LJ_SOFTFP && (ir+1)->o == IR_HIOP);
1179 if (!irt_ispri(ir->t)) {
1180 src = ra_alloc1(as, ir->op2, allow);
1181 rset_clear(allow, src);
1182 }
1183 if (hiop)
1184 type = ra_alloc1(as, (ir+1)->op2, allow);
1185 else
1186 type = ra_allock(as, (int32_t)irt_toitype(ir->t), allow);
1187 idx = asm_fuseahuref(as, ir->op1, &ofs, rset_exclude(allow, type), 4096);
1188 if (ra_hasreg(src)) emit_lso(as, ARMI_STR, src, idx, ofs);
1189 emit_lso(as, ARMI_STR, type, idx, ofs+4);
1190 }
1191 }
1192 }
1193
1194 static void asm_sload(ASMState *as, IRIns *ir)
1195 {
1196 int32_t ofs = 8*((int32_t)ir->op1-1) + ((ir->op2 & IRSLOAD_FRAME) ? 4 : 0);
1197 int hiop = (LJ_SOFTFP && (ir+1)->o == IR_HIOP);
1198 IRType t = hiop ? IRT_NUM : irt_type(ir->t);
1199 Reg dest = RID_NONE, type = RID_NONE, base;
1200 RegSet allow = RSET_GPR;
1201 lj_assertA(!(ir->op2 & IRSLOAD_PARENT),
1202 "bad parent SLOAD"); /* Handled by asm_head_side(). */
1203 lj_assertA(irt_isguard(ir->t) || !(ir->op2 & IRSLOAD_TYPECHECK),
1204 "inconsistent SLOAD variant");
1205 #if LJ_SOFTFP
1206 lj_assertA(!(ir->op2 & IRSLOAD_CONVERT),
1207 "unsplit SLOAD convert"); /* Handled by LJ_SOFTFP SPLIT. */
1208 if (hiop && ra_used(ir+1)) {
1209 type = ra_dest(as, ir+1, allow);
1210 rset_clear(allow, type);
1211 }
1212 #else
1213 if ((ir->op2 & IRSLOAD_CONVERT) && irt_isguard(ir->t) && t == IRT_INT) {
1214 dest = ra_scratch(as, RSET_FPR);
1215 asm_tointg(as, ir, dest);
1216 t = IRT_NUM; /* Continue with a regular number type check. */
1217 } else
1218 #endif
1219 if (ra_used(ir)) {
1220 Reg tmp = RID_NONE;
1221 if ((ir->op2 & IRSLOAD_CONVERT))
1222 tmp = ra_scratch(as, t == IRT_INT ? RSET_FPR : RSET_GPR);
1223 lj_assertA((LJ_SOFTFP ? 0 : irt_isnum(ir->t)) ||
1224 irt_isint(ir->t) || irt_isaddr(ir->t),
1225 "bad SLOAD type %d", irt_type(ir->t));
1226 dest = ra_dest(as, ir, (!LJ_SOFTFP && t == IRT_NUM) ? RSET_FPR : allow);
1227 rset_clear(allow, dest);
1228 base = ra_alloc1(as, REF_BASE, allow);
1229 if ((ir->op2 & IRSLOAD_CONVERT)) {
1230 if (t == IRT_INT) {
1231 emit_dn(as, ARMI_VMOV_R_S, dest, (tmp & 15));
1232 emit_dm(as, ARMI_VCVT_S32_F64, (tmp & 15), (tmp & 15));
1233 t = IRT_NUM; /* Check for original type. */
1234 } else {
1235 emit_dm(as, ARMI_VCVT_F64_S32, (dest & 15), (dest & 15));
1236 emit_dn(as, ARMI_VMOV_S_R, tmp, (dest & 15));
1237 t = IRT_INT; /* Check for original type. */
1238 }
1239 dest = tmp;
1240 }
1241 goto dotypecheck;
1242 }
1243 base = ra_alloc1(as, REF_BASE, allow);
1244 dotypecheck:
1245 rset_clear(allow, base);
1246 if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1247 if (ra_noreg(type)) {
1248 if (ofs < 256 && ra_hasreg(dest) && (dest & 1) == 0 &&
1249 rset_test((as->freeset & allow), dest+1)) {
1250 type = dest+1;
1251 ra_modified(as, type);
1252 } else {
1253 type = RID_TMP;
1254 }
1255 }
1256 asm_guardcc(as, t == IRT_NUM ? CC_HS : CC_NE);
1257 if ((ir->op2 & IRSLOAD_KEYINDEX)) {
1258 emit_n(as, ARMI_CMN|ARMI_K12|1, type);
1259 emit_dn(as, ARMI_EOR^emit_isk12(ARMI_EOR, ~LJ_KEYINDEX), type, type);
1260 } else {
1261 emit_n(as, ARMI_CMN|ARMI_K12|-irt_toitype_(t), type);
1262 }
1263 }
1264 if (ra_hasreg(dest)) {
1265 #if !LJ_SOFTFP
1266 if (t == IRT_NUM) {
1267 if (ofs < 1024) {
1268 emit_vlso(as, ARMI_VLDR_D, dest, base, ofs);
1269 } else {
1270 if (ra_hasreg(type)) emit_lso(as, ARMI_LDR, type, base, ofs+4);
1271 emit_vlso(as, ARMI_VLDR_D, dest, RID_TMP, 0);
1272 emit_opk(as, ARMI_ADD, RID_TMP, base, ofs, allow);
1273 return;
1274 }
1275 } else
1276 #endif
1277 emit_lso(as, ARMI_LDR, dest, base, ofs);
1278 }
1279 if (ra_hasreg(type)) emit_lso(as, ARMI_LDR, type, base, ofs+4);
1280 }
1281
1282 /* -- Allocations --------------------------------------------------------- */
1283
1284 #if LJ_HASFFI
1285 static void asm_cnew(ASMState *as, IRIns *ir)
1286 {
1287 CTState *cts = ctype_ctsG(J2G(as->J));
1288 CTypeID id = (CTypeID)IR(ir->op1)->i;
1289 CTSize sz;
1290 CTInfo info = lj_ctype_info(cts, id, &sz);
1291 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_mem_newgco];
1292 IRRef args[4];
1293 RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
1294 RegSet drop = RSET_SCRATCH;
1295 lj_assertA(sz != CTSIZE_INVALID || (ir->o == IR_CNEW && ir->op2 != REF_NIL),
1296 "bad CNEW/CNEWI operands");
1297
1298 as->gcsteps++;
1299 if (ra_hasreg(ir->r))
1300 rset_clear(drop, ir->r); /* Dest reg handled below. */
1301 ra_evictset(as, drop);
1302 if (ra_used(ir))
1303 ra_destreg(as, ir, RID_RET); /* GCcdata * */
1304
1305 /* Initialize immutable cdata object. */
1306 if (ir->o == IR_CNEWI) {
1307 int32_t ofs = sizeof(GCcdata);
1308 lj_assertA(sz == 4 || sz == 8, "bad CNEWI size %d", sz);
1309 if (sz == 8) {
1310 ofs += 4; ir++;
1311 lj_assertA(ir->o == IR_HIOP, "expected HIOP for CNEWI");
1312 }
1313 for (;;) {
1314 Reg r = ra_alloc1(as, ir->op2, allow);
1315 emit_lso(as, ARMI_STR, r, RID_RET, ofs);
1316 rset_clear(allow, r);
1317 if (ofs == sizeof(GCcdata)) break;
1318 ofs -= 4; ir--;
1319 }
1320 } else if (ir->op2 != REF_NIL) { /* Create VLA/VLS/aligned cdata. */
1321 ci = &lj_ir_callinfo[IRCALL_lj_cdata_newv];
1322 args[0] = ASMREF_L; /* lua_State *L */
1323 args[1] = ir->op1; /* CTypeID id */
1324 args[2] = ir->op2; /* CTSize sz */
1325 args[3] = ASMREF_TMP1; /* CTSize align */
1326 asm_gencall(as, ci, args);
1327 emit_loadi(as, ra_releasetmp(as, ASMREF_TMP1), (int32_t)ctype_align(info));
1328 return;
1329 }
1330
1331 /* Initialize gct and ctypeid. lj_mem_newgco() already sets marked. */
1332 {
1333 uint32_t k = emit_isk12(ARMI_MOV, id);
1334 Reg r = k ? RID_R1 : ra_allock(as, id, allow);
1335 emit_lso(as, ARMI_STRB, RID_TMP, RID_RET, offsetof(GCcdata, gct));
1336 emit_lsox(as, ARMI_STRH, r, RID_RET, offsetof(GCcdata, ctypeid));
1337 emit_d(as, ARMI_MOV|ARMI_K12|~LJ_TCDATA, RID_TMP);
1338 if (k) emit_d(as, ARMI_MOV^k, RID_R1);
1339 }
1340 args[0] = ASMREF_L; /* lua_State *L */
1341 args[1] = ASMREF_TMP1; /* MSize size */
1342 asm_gencall(as, ci, args);
1343 ra_allockreg(as, (int32_t)(sz+sizeof(GCcdata)),
1344 ra_releasetmp(as, ASMREF_TMP1));
1345 }
1346 #endif
1347
1348 /* -- Write barriers ------------------------------------------------------ */
1349
1350 static void asm_tbar(ASMState *as, IRIns *ir)
1351 {
1352 Reg tab = ra_alloc1(as, ir->op1, RSET_GPR);
1353 Reg link = ra_scratch(as, rset_exclude(RSET_GPR, tab));
1354 Reg gr = ra_allock(as, i32ptr(J2G(as->J)),
1355 rset_exclude(rset_exclude(RSET_GPR, tab), link));
1356 Reg mark = RID_TMP;
1357 MCLabel l_end = emit_label(as);
1358 emit_lso(as, ARMI_STR, link, tab, (int32_t)offsetof(GCtab, gclist));
1359 emit_lso(as, ARMI_STRB, mark, tab, (int32_t)offsetof(GCtab, marked));
1360 emit_lso(as, ARMI_STR, tab, gr,
1361 (int32_t)offsetof(global_State, gc.grayagain));
1362 emit_dn(as, ARMI_BIC|ARMI_K12|LJ_GC_BLACK, mark, mark);
1363 emit_lso(as, ARMI_LDR, link, gr,
1364 (int32_t)offsetof(global_State, gc.grayagain));
1365 emit_branch(as, ARMF_CC(ARMI_B, CC_EQ), l_end);
1366 emit_n(as, ARMI_TST|ARMI_K12|LJ_GC_BLACK, mark);
1367 emit_lso(as, ARMI_LDRB, mark, tab, (int32_t)offsetof(GCtab, marked));
1368 }
1369
1370 static void asm_obar(ASMState *as, IRIns *ir)
1371 {
1372 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_barrieruv];
1373 IRRef args[2];
1374 MCLabel l_end;
1375 Reg obj, val, tmp;
1376 /* No need for other object barriers (yet). */
1377 lj_assertA(IR(ir->op1)->o == IR_UREFC, "bad OBAR type");
1378 ra_evictset(as, RSET_SCRATCH);
1379 l_end = emit_label(as);
1380 args[0] = ASMREF_TMP1; /* global_State *g */
1381 args[1] = ir->op1; /* TValue *tv */
1382 asm_gencall(as, ci, args);
1383 if ((l_end[-1] >> 28) == CC_AL)
1384 l_end[-1] = ARMF_CC(l_end[-1], CC_NE);
1385 else
1386 emit_branch(as, ARMF_CC(ARMI_B, CC_EQ), l_end);
1387 ra_allockreg(as, i32ptr(J2G(as->J)), ra_releasetmp(as, ASMREF_TMP1));
1388 obj = IR(ir->op1)->r;
1389 tmp = ra_scratch(as, rset_exclude(RSET_GPR, obj));
1390 emit_n(as, ARMF_CC(ARMI_TST, CC_NE)|ARMI_K12|LJ_GC_BLACK, tmp);
1391 emit_n(as, ARMI_TST|ARMI_K12|LJ_GC_WHITES, RID_TMP);
1392 val = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, obj));
1393 emit_lso(as, ARMI_LDRB, tmp, obj,
1394 (int32_t)offsetof(GCupval, marked)-(int32_t)offsetof(GCupval, tv));
1395 emit_lso(as, ARMI_LDRB, RID_TMP, val, (int32_t)offsetof(GChead, marked));
1396 }
1397
1398 /* -- Arithmetic and logic operations ------------------------------------- */
1399
1400 #if !LJ_SOFTFP
1401 static void asm_fparith(ASMState *as, IRIns *ir, ARMIns ai)
1402 {
1403 Reg dest = ra_dest(as, ir, RSET_FPR);
1404 Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1405 right = (left >> 8); left &= 255;
1406 emit_dnm(as, ai, (dest & 15), (left & 15), (right & 15));
1407 }
1408
1409 static void asm_fpunary(ASMState *as, IRIns *ir, ARMIns ai)
1410 {
1411 Reg dest = ra_dest(as, ir, RSET_FPR);
1412 Reg left = ra_hintalloc(as, ir->op1, dest, RSET_FPR);
1413 emit_dm(as, ai, (dest & 15), (left & 15));
1414 }
1415
1416 static void asm_callround(ASMState *as, IRIns *ir, int id)
1417 {
1418 /* The modified regs must match with the *.dasc implementation. */
1419 RegSet drop = RID2RSET(RID_R0)|RID2RSET(RID_R1)|RID2RSET(RID_R2)|
1420 RID2RSET(RID_R3)|RID2RSET(RID_R12);
1421 RegSet of;
1422 Reg dest, src;
1423 ra_evictset(as, drop);
1424 dest = ra_dest(as, ir, RSET_FPR);
1425 emit_dnm(as, ARMI_VMOV_D_RR, RID_RETLO, RID_RETHI, (dest & 15));
1426 emit_call(as, id == IRFPM_FLOOR ? (void *)lj_vm_floor_sf :
1427 id == IRFPM_CEIL ? (void *)lj_vm_ceil_sf :
1428 (void *)lj_vm_trunc_sf);
1429 /* Workaround to protect argument GPRs from being used for remat. */
1430 of = as->freeset;
1431 as->freeset &= ~RSET_RANGE(RID_R0, RID_R1+1);
1432 as->cost[RID_R0] = as->cost[RID_R1] = REGCOST(~0u, ASMREF_L);
1433 src = ra_alloc1(as, ir->op1, RSET_FPR); /* May alloc GPR to remat FPR. */
1434 as->freeset |= (of & RSET_RANGE(RID_R0, RID_R1+1));
1435 emit_dnm(as, ARMI_VMOV_RR_D, RID_R0, RID_R1, (src & 15));
1436 }
1437
1438 static void asm_fpmath(ASMState *as, IRIns *ir)
1439 {
1440 if (ir->op2 <= IRFPM_TRUNC)
1441 asm_callround(as, ir, ir->op2);
1442 else if (ir->op2 == IRFPM_SQRT)
1443 asm_fpunary(as, ir, ARMI_VSQRT_D);
1444 else
1445 asm_callid(as, ir, IRCALL_lj_vm_floor + ir->op2);
1446 }
1447 #endif
1448
1449 static int asm_swapops(ASMState *as, IRRef lref, IRRef rref)
1450 {
1451 IRIns *ir;
1452 if (irref_isk(rref))
1453 return 0; /* Don't swap constants to the left. */
1454 if (irref_isk(lref))
1455 return 1; /* But swap constants to the right. */
1456 ir = IR(rref);
1457 if ((ir->o >= IR_BSHL && ir->o <= IR_BROR) ||
1458 (ir->o == IR_ADD && ir->op1 == ir->op2))
1459 return 0; /* Don't swap fusable operands to the left. */
1460 ir = IR(lref);
1461 if ((ir->o >= IR_BSHL && ir->o <= IR_BROR) ||
1462 (ir->o == IR_ADD && ir->op1 == ir->op2))
1463 return 1; /* But swap fusable operands to the right. */
1464 return 0; /* Otherwise don't swap. */
1465 }
1466
1467 static void asm_intop(ASMState *as, IRIns *ir, ARMIns ai)
1468 {
1469 IRRef lref = ir->op1, rref = ir->op2;
1470 Reg left, dest = ra_dest(as, ir, RSET_GPR);
1471 uint32_t m;
1472 if (asm_swapops(as, lref, rref)) {
1473 IRRef tmp = lref; lref = rref; rref = tmp;
1474 if ((ai & ~ARMI_S) == ARMI_SUB || (ai & ~ARMI_S) == ARMI_SBC)
1475 ai ^= (ARMI_SUB^ARMI_RSB);
1476 }
1477 left = ra_hintalloc(as, lref, dest, RSET_GPR);
1478 m = asm_fuseopm(as, ai, rref, rset_exclude(RSET_GPR, left));
1479 if (irt_isguard(ir->t)) { /* For IR_ADDOV etc. */
1480 asm_guardcc(as, CC_VS);
1481 ai |= ARMI_S;
1482 }
1483 emit_dn(as, ai^m, dest, left);
1484 }
1485
1486 /* Try to drop cmp r, #0. */
1487 static ARMIns asm_drop_cmp0(ASMState *as, ARMIns ai)
1488 {
1489 if (as->flagmcp == as->mcp) {
1490 uint32_t cc = (as->mcp[1] >> 28);
1491 as->flagmcp = NULL;
1492 if (cc <= CC_NE) {
1493 as->mcp++;
1494 ai |= ARMI_S;
1495 } else if (cc == CC_GE) {
1496 *++as->mcp ^= ((CC_GE^CC_PL) << 28);
1497 ai |= ARMI_S;
1498 } else if (cc == CC_LT) {
1499 *++as->mcp ^= ((CC_LT^CC_MI) << 28);
1500 ai |= ARMI_S;
1501 } /* else: other conds don't work in general. */
1502 }
1503 return ai;
1504 }
1505
1506 static void asm_intop_s(ASMState *as, IRIns *ir, ARMIns ai)
1507 {
1508 asm_intop(as, ir, asm_drop_cmp0(as, ai));
1509 }
1510
1511 static void asm_intneg(ASMState *as, IRIns *ir, ARMIns ai)
1512 {
1513 Reg dest = ra_dest(as, ir, RSET_GPR);
1514 Reg left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1515 emit_dn(as, ai|ARMI_K12|0, dest, left);
1516 }
1517
1518 /* NYI: use add/shift for MUL(OV) with constants. FOLD only does 2^k. */
1519 static void asm_intmul(ASMState *as, IRIns *ir)
1520 {
1521 Reg dest = ra_dest(as, ir, RSET_GPR);
1522 Reg left = ra_alloc1(as, ir->op1, rset_exclude(RSET_GPR, dest));
1523 Reg right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1524 Reg tmp = RID_NONE;
1525 /* ARMv5 restriction: dest != left and dest_hi != left. */
1526 if (dest == left && left != right) { left = right; right = dest; }
1527 if (irt_isguard(ir->t)) { /* IR_MULOV */
1528 if (!(as->flags & JIT_F_ARMV6) && dest == left)
1529 tmp = left = ra_scratch(as, rset_exclude(RSET_GPR, left));
1530 asm_guardcc(as, CC_NE);
1531 emit_nm(as, ARMI_TEQ|ARMF_SH(ARMSH_ASR, 31), RID_TMP, dest);
1532 emit_dnm(as, ARMI_SMULL|ARMF_S(right), dest, RID_TMP, left);
1533 } else {
1534 if (!(as->flags & JIT_F_ARMV6) && dest == left) tmp = left = RID_TMP;
1535 emit_nm(as, ARMI_MUL|ARMF_S(right), dest, left);
1536 }
1537 /* Only need this for the dest == left == right case. */
1538 if (ra_hasreg(tmp)) emit_dm(as, ARMI_MOV, tmp, right);
1539 }
1540
1541 static void asm_add(ASMState *as, IRIns *ir)
1542 {
1543 #if !LJ_SOFTFP
1544 if (irt_isnum(ir->t)) {
1545 if (!asm_fusemadd(as, ir, ARMI_VMLA_D, ARMI_VMLA_D))
1546 asm_fparith(as, ir, ARMI_VADD_D);
1547 return;
1548 }
1549 #endif
1550 asm_intop_s(as, ir, ARMI_ADD);
1551 }
1552
1553 static void asm_sub(ASMState *as, IRIns *ir)
1554 {
1555 #if !LJ_SOFTFP
1556 if (irt_isnum(ir->t)) {
1557 if (!asm_fusemadd(as, ir, ARMI_VNMLS_D, ARMI_VMLS_D))
1558 asm_fparith(as, ir, ARMI_VSUB_D);
1559 return;
1560 }
1561 #endif
1562 asm_intop_s(as, ir, ARMI_SUB);
1563 }
1564
1565 static void asm_mul(ASMState *as, IRIns *ir)
1566 {
1567 #if !LJ_SOFTFP
1568 if (irt_isnum(ir->t)) {
1569 asm_fparith(as, ir, ARMI_VMUL_D);
1570 return;
1571 }
1572 #endif
1573 asm_intmul(as, ir);
1574 }
1575
1576 #define asm_addov(as, ir) asm_add(as, ir)
1577 #define asm_subov(as, ir) asm_sub(as, ir)
1578 #define asm_mulov(as, ir) asm_mul(as, ir)
1579
1580 #if !LJ_SOFTFP
1581 #define asm_fpdiv(as, ir) asm_fparith(as, ir, ARMI_VDIV_D)
1582 #define asm_abs(as, ir) asm_fpunary(as, ir, ARMI_VABS_D)
1583 #endif
1584
1585 static void asm_neg(ASMState *as, IRIns *ir)
1586 {
1587 #if !LJ_SOFTFP
1588 if (irt_isnum(ir->t)) {
1589 asm_fpunary(as, ir, ARMI_VNEG_D);
1590 return;
1591 }
1592 #endif
1593 asm_intneg(as, ir, ARMI_RSB);
1594 }
1595
1596 static void asm_bitop(ASMState *as, IRIns *ir, ARMIns ai)
1597 {
1598 ai = asm_drop_cmp0(as, ai);
1599 if (ir->op2 == 0) {
1600 Reg dest = ra_dest(as, ir, RSET_GPR);
1601 uint32_t m = asm_fuseopm(as, ai, ir->op1, RSET_GPR);
1602 emit_d(as, ai^m, dest);
1603 } else {
1604 /* NYI: Turn BAND !k12 into uxtb, uxth or bfc or shl+shr. */
1605 asm_intop(as, ir, ai);
1606 }
1607 }
1608
1609 #define asm_bnot(as, ir) asm_bitop(as, ir, ARMI_MVN)
1610
1611 static void asm_bswap(ASMState *as, IRIns *ir)
1612 {
1613 Reg dest = ra_dest(as, ir, RSET_GPR);
1614 Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1615 if ((as->flags & JIT_F_ARMV6)) {
1616 emit_dm(as, ARMI_REV, dest, left);
1617 } else {
1618 Reg tmp2 = dest;
1619 if (tmp2 == left)
1620 tmp2 = ra_scratch(as, rset_exclude(rset_exclude(RSET_GPR, dest), left));
1621 emit_dnm(as, ARMI_EOR|ARMF_SH(ARMSH_LSR, 8), dest, tmp2, RID_TMP);
1622 emit_dm(as, ARMI_MOV|ARMF_SH(ARMSH_ROR, 8), tmp2, left);
1623 emit_dn(as, ARMI_BIC|ARMI_K12|256*8|255, RID_TMP, RID_TMP);
1624 emit_dnm(as, ARMI_EOR|ARMF_SH(ARMSH_ROR, 16), RID_TMP, left, left);
1625 }
1626 }
1627
1628 #define asm_band(as, ir) asm_bitop(as, ir, ARMI_AND)
1629 #define asm_bor(as, ir) asm_bitop(as, ir, ARMI_ORR)
1630 #define asm_bxor(as, ir) asm_bitop(as, ir, ARMI_EOR)
1631
1632 static void asm_bitshift(ASMState *as, IRIns *ir, ARMShift sh)
1633 {
1634 if (irref_isk(ir->op2)) { /* Constant shifts. */
1635 /* NYI: Turn SHL+SHR or BAND+SHR into uxtb, uxth or ubfx. */
1636 /* NYI: Turn SHL+ASR into sxtb, sxth or sbfx. */
1637 Reg dest = ra_dest(as, ir, RSET_GPR);
1638 Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1639 int32_t shift = (IR(ir->op2)->i & 31);
1640 emit_dm(as, ARMI_MOV|ARMF_SH(sh, shift), dest, left);
1641 } else {
1642 Reg dest = ra_dest(as, ir, RSET_GPR);
1643 Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1644 Reg right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1645 emit_dm(as, ARMI_MOV|ARMF_RSH(sh, right), dest, left);
1646 }
1647 }
1648
1649 #define asm_bshl(as, ir) asm_bitshift(as, ir, ARMSH_LSL)
1650 #define asm_bshr(as, ir) asm_bitshift(as, ir, ARMSH_LSR)
1651 #define asm_bsar(as, ir) asm_bitshift(as, ir, ARMSH_ASR)
1652 #define asm_bror(as, ir) asm_bitshift(as, ir, ARMSH_ROR)
1653 #define asm_brol(as, ir) lj_assertA(0, "unexpected BROL")
1654
1655 static void asm_intmin_max(ASMState *as, IRIns *ir, int cc)
1656 {
1657 uint32_t kcmp = 0, kmov = 0;
1658 Reg dest = ra_dest(as, ir, RSET_GPR);
1659 Reg left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1660 Reg right = 0;
1661 if (irref_isk(ir->op2)) {
1662 kcmp = emit_isk12(ARMI_CMP, IR(ir->op2)->i);
1663 if (kcmp) kmov = emit_isk12(ARMI_MOV, IR(ir->op2)->i);
1664 }
1665 if (!kmov) {
1666 kcmp = 0;
1667 right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1668 }
1669 if (kmov || dest != right) {
1670 emit_dm(as, ARMF_CC(ARMI_MOV, cc)^kmov, dest, right);
1671 cc ^= 1; /* Must use opposite conditions for paired moves. */
1672 } else {
1673 cc ^= (CC_LT^CC_GT); /* Otherwise may swap CC_LT <-> CC_GT. */
1674 }
1675 if (dest != left) emit_dm(as, ARMF_CC(ARMI_MOV, cc), dest, left);
1676 emit_nm(as, ARMI_CMP^kcmp, left, right);
1677 }
1678
1679 #if LJ_SOFTFP
1680 static void asm_sfpmin_max(ASMState *as, IRIns *ir, int cc)
1681 {
1682 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_softfp_cmp];
1683 RegSet drop = RSET_SCRATCH;
1684 Reg r;
1685 IRRef args[4];
1686 args[0] = ir->op1; args[1] = (ir+1)->op1;
1687 args[2] = ir->op2; args[3] = (ir+1)->op2;
1688 /* __aeabi_cdcmple preserves r0-r3. */
1689 if (ra_hasreg(ir->r)) rset_clear(drop, ir->r);
1690 if (ra_hasreg((ir+1)->r)) rset_clear(drop, (ir+1)->r);
1691 if (!rset_test(as->freeset, RID_R2) &&
1692 regcost_ref(as->cost[RID_R2]) == args[2]) rset_clear(drop, RID_R2);
1693 if (!rset_test(as->freeset, RID_R3) &&
1694 regcost_ref(as->cost[RID_R3]) == args[3]) rset_clear(drop, RID_R3);
1695 ra_evictset(as, drop);
1696 ra_destpair(as, ir);
1697 emit_dm(as, ARMF_CC(ARMI_MOV, cc), RID_RETHI, RID_R3);
1698 emit_dm(as, ARMF_CC(ARMI_MOV, cc), RID_RETLO, RID_R2);
1699 emit_call(as, (void *)ci->func);
1700 for (r = RID_R0; r <= RID_R3; r++)
1701 ra_leftov(as, r, args[r-RID_R0]);
1702 }
1703 #else
1704 static void asm_fpmin_max(ASMState *as, IRIns *ir, int cc)
1705 {
1706 Reg dest = (ra_dest(as, ir, RSET_FPR) & 15);
1707 Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1708 right = ((left >> 8) & 15); left &= 15;
1709 if (dest != left) emit_dm(as, ARMF_CC(ARMI_VMOV_D, cc^1), dest, left);
1710 if (dest != right) emit_dm(as, ARMF_CC(ARMI_VMOV_D, cc), dest, right);
1711 emit_d(as, ARMI_VMRS, 0);
1712 emit_dm(as, ARMI_VCMP_D, left, right);
1713 }
1714 #endif
1715
1716 static void asm_min_max(ASMState *as, IRIns *ir, int cc, int fcc)
1717 {
1718 #if LJ_SOFTFP
1719 UNUSED(fcc);
1720 #else
1721 if (irt_isnum(ir->t))
1722 asm_fpmin_max(as, ir, fcc);
1723 else
1724 #endif
1725 asm_intmin_max(as, ir, cc);
1726 }
1727
1728 #define asm_min(as, ir) asm_min_max(as, ir, CC_GT, CC_PL)
1729 #define asm_max(as, ir) asm_min_max(as, ir, CC_LT, CC_LE)
1730
1731 /* -- Comparisons --------------------------------------------------------- */
1732
1733 /* Map of comparisons to flags. ORDER IR. */
1734 static const uint8_t asm_compmap[IR_ABC+1] = {
1735 /* op FP swp int cc FP cc */
1736 /* LT */ CC_GE + (CC_HS << 4),
1737 /* GE x */ CC_LT + (CC_HI << 4),
1738 /* LE */ CC_GT + (CC_HI << 4),
1739 /* GT x */ CC_LE + (CC_HS << 4),
1740 /* ULT x */ CC_HS + (CC_LS << 4),
1741 /* UGE */ CC_LO + (CC_LO << 4),
1742 /* ULE x */ CC_HI + (CC_LO << 4),
1743 /* UGT */ CC_LS + (CC_LS << 4),
1744 /* EQ */ CC_NE + (CC_NE << 4),
1745 /* NE */ CC_EQ + (CC_EQ << 4),
1746 /* ABC */ CC_LS + (CC_LS << 4) /* Same as UGT. */
1747 };
1748
1749 #if LJ_SOFTFP
1750 /* FP comparisons. */
1751 static void asm_sfpcomp(ASMState *as, IRIns *ir)
1752 {
1753 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_softfp_cmp];
1754 RegSet drop = RSET_SCRATCH;
1755 Reg r;
1756 IRRef args[4];
1757 int swp = (((ir->o ^ (ir->o >> 2)) & ~(ir->o >> 3) & 1) << 1);
1758 args[swp^0] = ir->op1; args[swp^1] = (ir+1)->op1;
1759 args[swp^2] = ir->op2; args[swp^3] = (ir+1)->op2;
1760 /* __aeabi_cdcmple preserves r0-r3. This helps to reduce spills. */
1761 for (r = RID_R0; r <= RID_R3; r++)
1762 if (!rset_test(as->freeset, r) &&
1763 regcost_ref(as->cost[r]) == args[r-RID_R0]) rset_clear(drop, r);
1764 ra_evictset(as, drop);
1765 asm_guardcc(as, (asm_compmap[ir->o] >> 4));
1766 emit_call(as, (void *)ci->func);
1767 for (r = RID_R0; r <= RID_R3; r++)
1768 ra_leftov(as, r, args[r-RID_R0]);
1769 }
1770 #else
1771 /* FP comparisons. */
1772 static void asm_fpcomp(ASMState *as, IRIns *ir)
1773 {
1774 Reg left, right;
1775 ARMIns ai;
1776 int swp = ((ir->o ^ (ir->o >> 2)) & ~(ir->o >> 3) & 1);
1777 if (!swp && irref_isk(ir->op2) && ir_knum(IR(ir->op2))->u64 == 0) {
1778 left = (ra_alloc1(as, ir->op1, RSET_FPR) & 15);
1779 right = 0;
1780 ai = ARMI_VCMPZ_D;
1781 } else {
1782 left = ra_alloc2(as, ir, RSET_FPR);
1783 if (swp) {
1784 right = (left & 15); left = ((left >> 8) & 15);
1785 } else {
1786 right = ((left >> 8) & 15); left &= 15;
1787 }
1788 ai = ARMI_VCMP_D;
1789 }
1790 asm_guardcc(as, (asm_compmap[ir->o] >> 4));
1791 emit_d(as, ARMI_VMRS, 0);
1792 emit_dm(as, ai, left, right);
1793 }
1794 #endif
1795
1796 /* Integer comparisons. */
1797 static void asm_intcomp(ASMState *as, IRIns *ir)
1798 {
1799 ARMCC cc = (asm_compmap[ir->o] & 15);
1800 IRRef lref = ir->op1, rref = ir->op2;
1801 Reg left;
1802 uint32_t m;
1803 int cmpprev0 = 0;
1804 lj_assertA(irt_isint(ir->t) || irt_isu32(ir->t) || irt_isaddr(ir->t),
1805 "bad comparison data type %d", irt_type(ir->t));
1806 if (asm_swapops(as, lref, rref)) {
1807 Reg tmp = lref; lref = rref; rref = tmp;
1808 if (cc >= CC_GE) cc ^= 7; /* LT <-> GT, LE <-> GE */
1809 else if (cc > CC_NE) cc ^= 11; /* LO <-> HI, LS <-> HS */
1810 }
1811 if (irref_isk(rref) && IR(rref)->i == 0) {
1812 IRIns *irl = IR(lref);
1813 cmpprev0 = (irl+1 == ir);
1814 /* Combine comp(BAND(left, right), 0) into tst left, right. */
1815 if (cmpprev0 && irl->o == IR_BAND && !ra_used(irl)) {
1816 IRRef blref = irl->op1, brref = irl->op2;
1817 uint32_t m2 = 0;
1818 Reg bleft;
1819 if (asm_swapops(as, blref, brref)) {
1820 Reg tmp = blref; blref = brref; brref = tmp;
1821 }
1822 if (irref_isk(brref)) {
1823 m2 = emit_isk12(ARMI_AND, IR(brref)->i);
1824 if ((m2 & (ARMI_AND^ARMI_BIC)))
1825 goto notst; /* Not beneficial if we miss a constant operand. */
1826 }
1827 if (cc == CC_GE) cc = CC_PL;
1828 else if (cc == CC_LT) cc = CC_MI;
1829 else if (cc > CC_NE) goto notst; /* Other conds don't work with tst. */
1830 bleft = ra_alloc1(as, blref, RSET_GPR);
1831 if (!m2) m2 = asm_fuseopm(as, 0, brref, rset_exclude(RSET_GPR, bleft));
1832 asm_guardcc(as, cc);
1833 emit_n(as, ARMI_TST^m2, bleft);
1834 return;
1835 }
1836 }
1837 notst:
1838 left = ra_alloc1(as, lref, RSET_GPR);
1839 m = asm_fuseopm(as, ARMI_CMP, rref, rset_exclude(RSET_GPR, left));
1840 asm_guardcc(as, cc);
1841 emit_n(as, ARMI_CMP^m, left);
1842 /* Signed comparison with zero and referencing previous ins? */
1843 if (cmpprev0 && (cc <= CC_NE || cc >= CC_GE))
1844 as->flagmcp = as->mcp; /* Allow elimination of the compare. */
1845 }
1846
1847 static void asm_comp(ASMState *as, IRIns *ir)
1848 {
1849 #if !LJ_SOFTFP
1850 if (irt_isnum(ir->t))
1851 asm_fpcomp(as, ir);
1852 else
1853 #endif
1854 asm_intcomp(as, ir);
1855 }
1856
1857 #define asm_equal(as, ir) asm_comp(as, ir)
1858
1859 #if LJ_HASFFI
1860 /* 64 bit integer comparisons. */
1861 static void asm_int64comp(ASMState *as, IRIns *ir)
1862 {
1863 int signedcomp = (ir->o <= IR_GT);
1864 ARMCC cclo, cchi;
1865 Reg leftlo, lefthi;
1866 uint32_t mlo, mhi;
1867 RegSet allow = RSET_GPR, oldfree;
1868
1869 /* Always use unsigned comparison for loword. */
1870 cclo = asm_compmap[ir->o + (signedcomp ? 4 : 0)] & 15;
1871 leftlo = ra_alloc1(as, ir->op1, allow);
1872 oldfree = as->freeset;
1873 mlo = asm_fuseopm(as, ARMI_CMP, ir->op2, rset_clear(allow, leftlo));
1874 allow &= ~(oldfree & ~as->freeset); /* Update for allocs of asm_fuseopm. */
1875
1876 /* Use signed or unsigned comparison for hiword. */
1877 cchi = asm_compmap[ir->o] & 15;
1878 lefthi = ra_alloc1(as, (ir+1)->op1, allow);
1879 mhi = asm_fuseopm(as, ARMI_CMP, (ir+1)->op2, rset_clear(allow, lefthi));
1880
1881 /* All register allocations must be performed _before_ this point. */
1882 if (signedcomp) {
1883 MCLabel l_around = emit_label(as);
1884 asm_guardcc(as, cclo);
1885 emit_n(as, ARMI_CMP^mlo, leftlo);
1886 emit_branch(as, ARMF_CC(ARMI_B, CC_NE), l_around);
1887 if (cchi == CC_GE || cchi == CC_LE) cchi ^= 6; /* GE -> GT, LE -> LT */
1888 asm_guardcc(as, cchi);
1889 } else {
1890 asm_guardcc(as, cclo);
1891 emit_n(as, ARMF_CC(ARMI_CMP, CC_EQ)^mlo, leftlo);
1892 }
1893 emit_n(as, ARMI_CMP^mhi, lefthi);
1894 }
1895 #endif
1896
1897 /* -- Split register ops -------------------------------------------------- */
1898
1899 /* Hiword op of a split 32/32 bit op. Previous op is the loword op. */
1900 static void asm_hiop(ASMState *as, IRIns *ir)
1901 {
1902 /* HIOP is marked as a store because it needs its own DCE logic. */
1903 int uselo = ra_used(ir-1), usehi = ra_used(ir); /* Loword/hiword used? */
1904 if (LJ_UNLIKELY(!(as->flags & JIT_F_OPT_DCE))) uselo = usehi = 1;
1905 #if LJ_HASFFI || LJ_SOFTFP
1906 if ((ir-1)->o <= IR_NE) { /* 64 bit integer or FP comparisons. ORDER IR. */
1907 as->curins--; /* Always skip the loword comparison. */
1908 #if LJ_SOFTFP
1909 if (!irt_isint(ir->t)) {
1910 asm_sfpcomp(as, ir-1);
1911 return;
1912 }
1913 #endif
1914 #if LJ_HASFFI
1915 asm_int64comp(as, ir-1);
1916 #endif
1917 return;
1918 #if LJ_SOFTFP
1919 } else if ((ir-1)->o == IR_MIN || (ir-1)->o == IR_MAX) {
1920 as->curins--; /* Always skip the loword min/max. */
1921 if (uselo || usehi)
1922 asm_sfpmin_max(as, ir-1, (ir-1)->o == IR_MIN ? CC_PL : CC_LE);
1923 return;
1924 #elif LJ_HASFFI
1925 } else if ((ir-1)->o == IR_CONV) {
1926 as->curins--; /* Always skip the CONV. */
1927 if (usehi || uselo)
1928 asm_conv64(as, ir);
1929 return;
1930 #endif
1931 } else if ((ir-1)->o == IR_XSTORE) {
1932 if ((ir-1)->r != RID_SINK)
1933 asm_xstore_(as, ir, 4);
1934 return;
1935 }
1936 #endif
1937 if (!usehi) return; /* Skip unused hiword op for all remaining ops. */
1938 switch ((ir-1)->o) {
1939 #if LJ_HASFFI
1940 case IR_ADD:
1941 as->curins--;
1942 asm_intop(as, ir, ARMI_ADC);
1943 asm_intop(as, ir-1, ARMI_ADD|ARMI_S);
1944 break;
1945 case IR_SUB:
1946 as->curins--;
1947 asm_intop(as, ir, ARMI_SBC);
1948 asm_intop(as, ir-1, ARMI_SUB|ARMI_S);
1949 break;
1950 case IR_NEG:
1951 as->curins--;
1952 asm_intneg(as, ir, ARMI_RSC);
1953 asm_intneg(as, ir-1, ARMI_RSB|ARMI_S);
1954 break;
1955 case IR_CNEWI:
1956 /* Nothing to do here. Handled by lo op itself. */
1957 break;
1958 #endif
1959 #if LJ_SOFTFP
1960 case IR_SLOAD: case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
1961 case IR_STRTO:
1962 if (!uselo)
1963 ra_allocref(as, ir->op1, RSET_GPR); /* Mark lo op as used. */
1964 break;
1965 case IR_ASTORE: case IR_HSTORE: case IR_USTORE: case IR_TOSTR: case IR_TMPREF:
1966 /* Nothing to do here. Handled by lo op itself. */
1967 break;
1968 #endif
1969 case IR_CALLN: case IR_CALLL: case IR_CALLS: case IR_CALLXS:
1970 if (!uselo)
1971 ra_allocref(as, ir->op1, RID2RSET(RID_RETLO)); /* Mark lo op as used. */
1972 break;
1973 default: lj_assertA(0, "bad HIOP for op %d", (ir-1)->o); break;
1974 }
1975 }
1976
1977 /* -- Profiling ----------------------------------------------------------- */
1978
1979 static void asm_prof(ASMState *as, IRIns *ir)
1980 {
1981 UNUSED(ir);
1982 asm_guardcc(as, CC_NE);
1983 emit_n(as, ARMI_TST|ARMI_K12|HOOK_PROFILE, RID_TMP);
1984 emit_lsptr(as, ARMI_LDRB, RID_TMP, (void *)&J2G(as->J)->hookmask);
1985 }
1986
1987 /* -- Stack handling ------------------------------------------------------ */
1988
1989 /* Check Lua stack size for overflow. Use exit handler as fallback. */
1990 static void asm_stack_check(ASMState *as, BCReg topslot,
1991 IRIns *irp, RegSet allow, ExitNo exitno)
1992 {
1993 Reg pbase;
1994 uint32_t k;
1995 if (irp) {
1996 if (!ra_hasspill(irp->s)) {
1997 pbase = irp->r;
1998 lj_assertA(ra_hasreg(pbase), "base reg lost");
1999 } else if (allow) {
2000 pbase = rset_pickbot(allow);
2001 } else {
2002 pbase = RID_RET;
2003 emit_lso(as, ARMI_LDR, RID_RET, RID_SP, 0); /* Restore temp. register. */
2004 }
2005 } else {
2006 pbase = RID_BASE;
2007 }
2008 emit_branch(as, ARMF_CC(ARMI_BL, CC_LS), exitstub_addr(as->J, exitno));
2009 k = emit_isk12(0, (int32_t)(8*topslot));
2010 lj_assertA(k, "slot offset %d does not fit in K12", 8*topslot);
2011 emit_n(as, ARMI_CMP^k, RID_TMP);
2012 emit_dnm(as, ARMI_SUB, RID_TMP, RID_TMP, pbase);
2013 emit_lso(as, ARMI_LDR, RID_TMP, RID_TMP,
2014 (int32_t)offsetof(lua_State, maxstack));
2015 if (irp) { /* Must not spill arbitrary registers in head of side trace. */
2016 int32_t i = i32ptr(&J2G(as->J)->cur_L);
2017 if (ra_hasspill(irp->s))
2018 emit_lso(as, ARMI_LDR, pbase, RID_SP, sps_scale(irp->s));
2019 emit_lso(as, ARMI_LDR, RID_TMP, RID_TMP, (i & 4095));
2020 if (ra_hasspill(irp->s) && !allow)
2021 emit_lso(as, ARMI_STR, RID_RET, RID_SP, 0); /* Save temp. register. */
2022 emit_loadi(as, RID_TMP, (i & ~4095));
2023 } else {
2024 emit_getgl(as, RID_TMP, cur_L);
2025 }
2026 }
2027
2028 /* Restore Lua stack from on-trace state. */
2029 static void asm_stack_restore(ASMState *as, SnapShot *snap)
2030 {
2031 SnapEntry *map = &as->T->snapmap[snap->mapofs];
2032 SnapEntry *flinks = &as->T->snapmap[snap_nextofs(as->T, snap)-1];
2033 MSize n, nent = snap->nent;
2034 /* Store the value of all modified slots to the Lua stack. */
2035 for (n = 0; n < nent; n++) {
2036 SnapEntry sn = map[n];
2037 BCReg s = snap_slot(sn);
2038 int32_t ofs = 8*((int32_t)s-1);
2039 IRRef ref = snap_ref(sn);
2040 IRIns *ir = IR(ref);
2041 if ((sn & SNAP_NORESTORE))
2042 continue;
2043 if (irt_isnum(ir->t)) {
2044 #if LJ_SOFTFP
2045 RegSet odd = rset_exclude(RSET_GPRODD, RID_BASE);
2046 Reg tmp;
2047 /* LJ_SOFTFP: must be a number constant. */
2048 lj_assertA(irref_isk(ref), "unsplit FP op");
2049 tmp = ra_allock(as, (int32_t)ir_knum(ir)->u32.lo,
2050 rset_exclude(RSET_GPREVEN, RID_BASE));
2051 emit_lso(as, ARMI_STR, tmp, RID_BASE, ofs);
2052 if (rset_test(as->freeset, tmp+1)) odd = RID2RSET(tmp+1);
2053 tmp = ra_allock(as, (int32_t)ir_knum(ir)->u32.hi, odd);
2054 emit_lso(as, ARMI_STR, tmp, RID_BASE, ofs+4);
2055 #else
2056 Reg src = ra_alloc1(as, ref, RSET_FPR);
2057 emit_vlso(as, ARMI_VSTR_D, src, RID_BASE, ofs);
2058 #endif
2059 } else {
2060 RegSet odd = rset_exclude(RSET_GPRODD, RID_BASE);
2061 Reg type;
2062 lj_assertA(irt_ispri(ir->t) || irt_isaddr(ir->t) || irt_isinteger(ir->t),
2063 "restore of IR type %d", irt_type(ir->t));
2064 if (!irt_ispri(ir->t)) {
2065 Reg src = ra_alloc1(as, ref, rset_exclude(RSET_GPREVEN, RID_BASE));
2066 emit_lso(as, ARMI_STR, src, RID_BASE, ofs);
2067 if (rset_test(as->freeset, src+1)) odd = RID2RSET(src+1);
2068 }
2069 if ((sn & (SNAP_CONT|SNAP_FRAME))) {
2070 if (s == 0) continue; /* Do not overwrite link to previous frame. */
2071 type = ra_allock(as, (int32_t)(*flinks--), odd);
2072 #if LJ_SOFTFP
2073 } else if ((sn & SNAP_SOFTFPNUM)) {
2074 type = ra_alloc1(as, ref+1, rset_exclude(RSET_GPRODD, RID_BASE));
2075 #endif
2076 } else if ((sn & SNAP_KEYINDEX)) {
2077 type = ra_allock(as, (int32_t)LJ_KEYINDEX, odd);
2078 } else {
2079 type = ra_allock(as, (int32_t)irt_toitype(ir->t), odd);
2080 }
2081 emit_lso(as, ARMI_STR, type, RID_BASE, ofs+4);
2082 }
2083 checkmclim(as);
2084 }
2085 lj_assertA(map + nent == flinks, "inconsistent frames in snapshot");
2086 }
2087
2088 /* -- GC handling --------------------------------------------------------- */
2089
2090 /* Marker to prevent patching the GC check exit. */
2091 #define ARM_NOPATCH_GC_CHECK (ARMI_BIC|ARMI_K12)
2092
2093 /* Check GC threshold and do one or more GC steps. */
2094 static void asm_gc_check(ASMState *as)
2095 {
2096 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_step_jit];
2097 IRRef args[2];
2098 MCLabel l_end;
2099 Reg tmp1, tmp2;
2100 ra_evictset(as, RSET_SCRATCH);
2101 l_end = emit_label(as);
2102 /* Exit trace if in GCSatomic or GCSfinalize. Avoids syncing GC objects. */
2103 asm_guardcc(as, CC_NE); /* Assumes asm_snap_prep() already done. */
2104 *--as->mcp = ARM_NOPATCH_GC_CHECK;
2105 emit_n(as, ARMI_CMP|ARMI_K12|0, RID_RET);
2106 args[0] = ASMREF_TMP1; /* global_State *g */
2107 args[1] = ASMREF_TMP2; /* MSize steps */
2108 asm_gencall(as, ci, args);
2109 tmp1 = ra_releasetmp(as, ASMREF_TMP1);
2110 tmp2 = ra_releasetmp(as, ASMREF_TMP2);
2111 emit_loadi(as, tmp2, as->gcsteps);
2112 /* Jump around GC step if GC total < GC threshold. */
2113 emit_branch(as, ARMF_CC(ARMI_B, CC_LS), l_end);
2114 emit_nm(as, ARMI_CMP, RID_TMP, tmp2);
2115 emit_lso(as, ARMI_LDR, tmp2, tmp1,
2116 (int32_t)offsetof(global_State, gc.threshold));
2117 emit_lso(as, ARMI_LDR, RID_TMP, tmp1,
2118 (int32_t)offsetof(global_State, gc.total));
2119 ra_allockreg(as, i32ptr(J2G(as->J)), tmp1);
2120 as->gcsteps = 0;
2121 checkmclim(as);
2122 }
2123
2124 /* -- Loop handling ------------------------------------------------------- */
2125
2126 /* Fixup the loop branch. */
2127 static void asm_loop_fixup(ASMState *as)
2128 {
2129 MCode *p = as->mctop;
2130 MCode *target = as->mcp;
2131 if (as->loopinv) { /* Inverted loop branch? */
2132 /* asm_guardcc already inverted the bcc and patched the final bl. */
2133 p[-2] |= ((uint32_t)(target-p) & 0x00ffffffu);
2134 } else {
2135 p[-1] = ARMI_B | ((uint32_t)((target-p)-1) & 0x00ffffffu);
2136 }
2137 }
2138
2139 /* Fixup the tail of the loop. */
2140 static void asm_loop_tail_fixup(ASMState *as)
2141 {
2142 UNUSED(as); /* Nothing to do. */
2143 }
2144
2145 /* -- Head of trace ------------------------------------------------------- */
2146
2147 /* Reload L register from g->cur_L. */
2148 static void asm_head_lreg(ASMState *as)
2149 {
2150 IRIns *ir = IR(ASMREF_L);
2151 if (ra_used(ir)) {
2152 Reg r = ra_dest(as, ir, RSET_GPR);
2153 emit_getgl(as, r, cur_L);
2154 ra_evictk(as);
2155 }
2156 }
2157
2158 /* Coalesce BASE register for a root trace. */
2159 static void asm_head_root_base(ASMState *as)
2160 {
2161 IRIns *ir;
2162 asm_head_lreg(as);
2163 ir = IR(REF_BASE);
2164 if (ra_hasreg(ir->r) && (rset_test(as->modset, ir->r) || irt_ismarked(ir->t)))
2165 ra_spill(as, ir);
2166 ra_destreg(as, ir, RID_BASE);
2167 }
2168
2169 /* Coalesce BASE register for a side trace. */
2170 static Reg asm_head_side_base(ASMState *as, IRIns *irp)
2171 {
2172 IRIns *ir;
2173 asm_head_lreg(as);
2174 ir = IR(REF_BASE);
2175 if (ra_hasreg(ir->r) && (rset_test(as->modset, ir->r) || irt_ismarked(ir->t)))
2176 ra_spill(as, ir);
2177 if (ra_hasspill(irp->s)) {
2178 return ra_dest(as, ir, RSET_GPR);
2179 } else {
2180 Reg r = irp->r;
2181 lj_assertA(ra_hasreg(r), "base reg lost");
2182 if (r != ir->r && !rset_test(as->freeset, r))
2183 ra_restore(as, regcost_ref(as->cost[r]));
2184 ra_destreg(as, ir, r);
2185 return r;
2186 }
2187 }
2188
2189 /* -- Tail of trace ------------------------------------------------------- */
2190
2191 /* Fixup the tail code. */
2192 static void asm_tail_fixup(ASMState *as, TraceNo lnk)
2193 {
2194 MCode *p = as->mctop;
2195 MCode *target;
2196 int32_t spadj = as->T->spadjust;
2197 if (spadj == 0) {
2198 as->mctop = --p;
2199 } else {
2200 /* Patch stack adjustment. */
2201 uint32_t k = emit_isk12(ARMI_ADD, spadj);
2202 lj_assertA(k, "stack adjustment %d does not fit in K12", spadj);
2203 p[-2] = (ARMI_ADD^k) | ARMF_D(RID_SP) | ARMF_N(RID_SP);
2204 }
2205 /* Patch exit branch. */
2206 target = lnk ? traceref(as->J, lnk)->mcode : (MCode *)lj_vm_exit_interp;
2207 p[-1] = ARMI_B|(((target-p)-1)&0x00ffffffu);
2208 }
2209
2210 /* Prepare tail of code. */
2211 static void asm_tail_prep(ASMState *as)
2212 {
2213 MCode *p = as->mctop - 1; /* Leave room for exit branch. */
2214 if (as->loopref) {
2215 as->invmcp = as->mcp = p;
2216 } else {
2217 as->mcp = p-1; /* Leave room for stack pointer adjustment. */
2218 as->invmcp = NULL;
2219 }
2220 *p = 0; /* Prevent load/store merging. */
2221 }
2222
2223 /* -- Trace setup --------------------------------------------------------- */
2224
2225 /* Ensure there are enough stack slots for call arguments. */
2226 static Reg asm_setup_call_slots(ASMState *as, IRIns *ir, const CCallInfo *ci)
2227 {
2228 IRRef args[CCI_NARGS_MAX*2];
2229 uint32_t i, nargs = CCI_XNARGS(ci);
2230 int nslots = 0, ngpr = REGARG_NUMGPR, nfpr = REGARG_NUMFPR, fprodd = 0;
2231 asm_collectargs(as, ir, ci, args);
2232 for (i = 0; i < nargs; i++) {
2233 if (!LJ_SOFTFP && args[i] && irt_isfp(IR(args[i])->t)) {
2234 if (!LJ_ABI_SOFTFP && !(ci->flags & CCI_VARARG)) {
2235 if (irt_isnum(IR(args[i])->t)) {
2236 if (nfpr > 0) nfpr--;
2237 else fprodd = 0, nslots = (nslots + 3) & ~1;
2238 } else {
2239 if (fprodd) fprodd--;
2240 else if (nfpr > 0) fprodd = 1, nfpr--;
2241 else nslots++;
2242 }
2243 } else if (irt_isnum(IR(args[i])->t)) {
2244 ngpr &= ~1;
2245 if (ngpr > 0) ngpr -= 2; else nslots += 2;
2246 } else {
2247 if (ngpr > 0) ngpr--; else nslots++;
2248 }
2249 } else {
2250 if (ngpr > 0) ngpr--; else nslots++;
2251 }
2252 }
2253 if (nslots > as->evenspill) /* Leave room for args in stack slots. */
2254 as->evenspill = nslots;
2255 return REGSP_HINT(RID_RET);
2256 }
2257
2258 static void asm_setup_target(ASMState *as)
2259 {
2260 /* May need extra exit for asm_stack_check on side traces. */
2261 asm_exitstub_setup(as, as->T->nsnap + (as->parent ? 1 : 0));
2262 }
2263
2264 /* -- Trace patching ------------------------------------------------------ */
2265
2266 /* Patch exit jumps of existing machine code to a new target. */
2267 void lj_asm_patchexit(jit_State *J, GCtrace *T, ExitNo exitno, MCode *target)
2268 {
2269 MCode *p = T->mcode;
2270 MCode *pe = (MCode *)((char *)p + T->szmcode);
2271 MCode *cstart = NULL, *cend = p;
2272 MCode *mcarea = lj_mcode_patch(J, p, 0);
2273 MCode *px = exitstub_addr(J, exitno) - 2;
2274 for (; p < pe; p++) {
2275 /* Look for bl_cc exitstub, replace with b_cc target. */
2276 uint32_t ins = *p;
2277 if ((ins & 0x0f000000u) == 0x0b000000u && ins < 0xf0000000u &&
2278 ((ins ^ (px-p)) & 0x00ffffffu) == 0 &&
2279 p[-1] != ARM_NOPATCH_GC_CHECK) {
2280 *p = (ins & 0xfe000000u) | (((target-p)-2) & 0x00ffffffu);
2281 cend = p+1;
2282 if (!cstart) cstart = p;
2283 }
2284 }
2285 lj_assertJ(cstart != NULL, "exit stub %d not found", exitno);
2286 lj_mcode_sync(cstart, cend);
2287 lj_mcode_patch(J, mcarea, 1);
2288 }
2289