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annotate third_party/luajit/src/lj_opt_sink.c @ 185:dfdd66825396

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Merged in keep alive changes and mrjunejune changes.
author MrJuneJune <me@mrjunejune.com>
date Fri, 23 Jan 2026 22:22:30 -0800
parents 94705b5986b3
children
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rev   line source
178
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1 /*
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2 ** SINK: Allocation Sinking and Store Sinking.
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3 ** Copyright (C) 2005-2023 Mike Pall. See Copyright Notice in luajit.h
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4 */
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5
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6 #define lj_opt_sink_c
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7 #define LUA_CORE
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8
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9 #include "lj_obj.h"
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10
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11 #if LJ_HASJIT
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12
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13 #include "lj_ir.h"
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14 #include "lj_jit.h"
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15 #include "lj_iropt.h"
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16 #include "lj_target.h"
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17
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18 /* Some local macros to save typing. Undef'd at the end. */
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19 #define IR(ref) (&J->cur.ir[(ref)])
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20
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21 /* Check whether the store ref points to an eligible allocation. */
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22 static IRIns *sink_checkalloc(jit_State *J, IRIns *irs)
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23 {
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24 IRIns *ir = IR(irs->op1);
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25 if (!irref_isk(ir->op2))
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26 return NULL; /* Non-constant key. */
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27 if (ir->o == IR_HREFK || ir->o == IR_AREF)
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28 ir = IR(ir->op1);
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29 else if (!(ir->o == IR_HREF || ir->o == IR_NEWREF ||
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30 ir->o == IR_FREF || ir->o == IR_ADD))
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31 return NULL; /* Unhandled reference type (for XSTORE). */
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32 ir = IR(ir->op1);
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33 if (!(ir->o == IR_TNEW || ir->o == IR_TDUP || ir->o == IR_CNEW))
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34 return NULL; /* Not an allocation. */
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35 return ir; /* Return allocation. */
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36 }
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37
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38 /* Recursively check whether a value depends on a PHI. */
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39 static int sink_phidep(jit_State *J, IRRef ref, int *workp)
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40 {
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41 IRIns *ir = IR(ref);
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42 if (!*workp) return 1; /* Give up and pretend it does. */
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43 (*workp)--;
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44 if (irt_isphi(ir->t)) return 1;
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45 if (ir->op1 >= REF_FIRST && sink_phidep(J, ir->op1, workp)) return 1;
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46 if (ir->op2 >= REF_FIRST && sink_phidep(J, ir->op2, workp)) return 1;
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47 return 0;
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48 }
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49
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50 /* Check whether a value is a sinkable PHI or loop-invariant. */
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51 static int sink_checkphi(jit_State *J, IRIns *ira, IRRef ref)
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52 {
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53 if (ref >= REF_FIRST) {
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54 IRIns *ir = IR(ref);
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55 if (irt_isphi(ir->t) || (ir->o == IR_CONV && ir->op2 == IRCONV_NUM_INT &&
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56 irt_isphi(IR(ir->op1)->t))) {
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57 ira->prev++;
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58 return 1; /* Sinkable PHI. */
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59 }
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60 /* Otherwise the value must be loop-invariant. */
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61 if (ref < J->loopref) {
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62 /* Check for PHI dependencies, but give up after reasonable effort. */
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63 int work = 64;
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64 return !sink_phidep(J, ref, &work);
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65 } else {
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66 return 0; /* Loop-variant. */
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67 }
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68 }
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69 return 1; /* Constant (non-PHI). */
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70 }
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71
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72 /* Mark non-sinkable allocations using single-pass backward propagation.
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73 **
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74 ** Roots for the marking process are:
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75 ** - Some PHIs or snapshots (see below).
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76 ** - Non-PHI, non-constant values stored to PHI allocations.
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77 ** - All guards.
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78 ** - Any remaining loads not eliminated by store-to-load forwarding.
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79 ** - Stores with non-constant keys.
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80 ** - All stored values.
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81 */
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82 static void sink_mark_ins(jit_State *J)
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83 {
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84 IRIns *ir, *irlast = IR(J->cur.nins-1);
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85 for (ir = irlast ; ; ir--) {
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86 switch (ir->o) {
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87 case IR_BASE:
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88 return; /* Finished. */
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89 case IR_ALOAD: case IR_HLOAD: case IR_XLOAD: case IR_TBAR: case IR_ALEN:
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90 irt_setmark(IR(ir->op1)->t); /* Mark ref for remaining loads. */
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91 break;
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92 case IR_FLOAD:
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93 if (irt_ismarked(ir->t) || ir->op2 == IRFL_TAB_META)
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94 irt_setmark(IR(ir->op1)->t); /* Mark table for remaining loads. */
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95 break;
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96 case IR_ASTORE: case IR_HSTORE: case IR_FSTORE: case IR_XSTORE: {
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97 IRIns *ira = sink_checkalloc(J, ir);
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98 if (!ira || (irt_isphi(ira->t) && !sink_checkphi(J, ira, ir->op2)))
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99 irt_setmark(IR(ir->op1)->t); /* Mark ineligible ref. */
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100 irt_setmark(IR(ir->op2)->t); /* Mark stored value. */
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101 break;
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102 }
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103 #if LJ_HASFFI
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104 case IR_CNEWI:
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105 if (irt_isphi(ir->t) &&
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106 (!sink_checkphi(J, ir, ir->op2) ||
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107 (LJ_32 && ir+1 < irlast && (ir+1)->o == IR_HIOP &&
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108 !sink_checkphi(J, ir, (ir+1)->op2))))
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109 irt_setmark(ir->t); /* Mark ineligible allocation. */
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110 #endif
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111 /* fallthrough */
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112 case IR_USTORE:
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113 irt_setmark(IR(ir->op2)->t); /* Mark stored value. */
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114 break;
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115 #if LJ_HASFFI
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116 case IR_CALLXS:
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117 #endif
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118 case IR_CALLS:
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119 irt_setmark(IR(ir->op1)->t); /* Mark (potentially) stored values. */
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120 break;
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121 case IR_PHI: {
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122 IRIns *irl = IR(ir->op1), *irr = IR(ir->op2);
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123 irl->prev = irr->prev = 0; /* Clear PHI value counts. */
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124 if (irl->o == irr->o &&
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125 (irl->o == IR_TNEW || irl->o == IR_TDUP ||
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
126 (LJ_HASFFI && (irl->o == IR_CNEW || irl->o == IR_CNEWI))))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
127 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
128 irt_setmark(irl->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
129 irt_setmark(irr->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
130 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
131 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
132 default:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
133 if (irt_ismarked(ir->t) || irt_isguard(ir->t)) { /* Propagate mark. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
134 if (ir->op1 >= REF_FIRST) irt_setmark(IR(ir->op1)->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
135 if (ir->op2 >= REF_FIRST) irt_setmark(IR(ir->op2)->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
136 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
137 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
138 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
139 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
140 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
141
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
142 /* Mark all instructions referenced by a snapshot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
143 static void sink_mark_snap(jit_State *J, SnapShot *snap)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
144 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
145 SnapEntry *map = &J->cur.snapmap[snap->mapofs];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
146 MSize n, nent = snap->nent;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
147 for (n = 0; n < nent; n++) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
148 IRRef ref = snap_ref(map[n]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
149 if (!irref_isk(ref))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
150 irt_setmark(IR(ref)->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
151 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
152 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
153
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
154 /* Iteratively remark PHI refs with differing marks or PHI value counts. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
155 static void sink_remark_phi(jit_State *J)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
156 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
157 IRIns *ir;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
158 int remark;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
159 do {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
160 remark = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
161 for (ir = IR(J->cur.nins-1); ir->o == IR_PHI; ir--) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
162 IRIns *irl = IR(ir->op1), *irr = IR(ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
163 if (!((irl->t.irt ^ irr->t.irt) & IRT_MARK) && irl->prev == irr->prev)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
164 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
165 remark |= (~(irl->t.irt & irr->t.irt) & IRT_MARK);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
166 irt_setmark(IR(ir->op1)->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
167 irt_setmark(IR(ir->op2)->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
168 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
169 } while (remark);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
170 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
171
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
172 /* Sweep instructions and tag sunken allocations and stores. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
173 static void sink_sweep_ins(jit_State *J)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
174 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
175 IRIns *ir, *irbase = IR(REF_BASE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
176 for (ir = IR(J->cur.nins-1) ; ir >= irbase; ir--) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
177 switch (ir->o) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
178 case IR_ASTORE: case IR_HSTORE: case IR_FSTORE: case IR_XSTORE: {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
179 IRIns *ira = sink_checkalloc(J, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
180 if (ira && !irt_ismarked(ira->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
181 int delta = (int)(ir - ira);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
182 ir->prev = REGSP(RID_SINK, delta > 255 ? 255 : delta);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
183 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
184 ir->prev = REGSP_INIT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
185 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
186 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
187 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
188 case IR_NEWREF:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
189 if (!irt_ismarked(IR(ir->op1)->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
190 ir->prev = REGSP(RID_SINK, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
191 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
192 irt_clearmark(ir->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
193 ir->prev = REGSP_INIT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
194 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
195 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
196 #if LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
197 case IR_CNEW: case IR_CNEWI:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
198 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
199 case IR_TNEW: case IR_TDUP:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
200 if (!irt_ismarked(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
201 ir->t.irt &= ~IRT_GUARD;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
202 ir->prev = REGSP(RID_SINK, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
203 J->cur.sinktags = 1; /* Signal present SINK tags to assembler. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
204 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
205 irt_clearmark(ir->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
206 ir->prev = REGSP_INIT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
207 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
208 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
209 case IR_PHI: {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
210 IRIns *ira = IR(ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
211 if (!irt_ismarked(ira->t) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
212 (ira->o == IR_TNEW || ira->o == IR_TDUP ||
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
213 (LJ_HASFFI && (ira->o == IR_CNEW || ira->o == IR_CNEWI)))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
214 ir->prev = REGSP(RID_SINK, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
215 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
216 ir->prev = REGSP_INIT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
217 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
218 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
219 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
220 default:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
221 irt_clearmark(ir->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
222 ir->prev = REGSP_INIT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
223 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
224 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
225 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
226 for (ir = IR(J->cur.nk); ir < irbase; ir++) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
227 irt_clearmark(ir->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
228 ir->prev = REGSP_INIT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
229 /* The false-positive of irt_is64() for ASMREF_L (REF_NIL) is OK here. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
230 if (irt_is64(ir->t) && ir->o != IR_KNULL)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
231 ir++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
232 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
233 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
234
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
235 /* Allocation sinking and store sinking.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
236 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
237 ** 1. Mark all non-sinkable allocations.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
238 ** 2. Then sink all remaining allocations and the related stores.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
239 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
240 void lj_opt_sink(jit_State *J)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
241 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
242 const uint32_t need = (JIT_F_OPT_SINK|JIT_F_OPT_FWD|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
243 JIT_F_OPT_DCE|JIT_F_OPT_CSE|JIT_F_OPT_FOLD);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
244 if ((J->flags & need) == need &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
245 (J->chain[IR_TNEW] || J->chain[IR_TDUP] ||
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
246 (LJ_HASFFI && (J->chain[IR_CNEW] || J->chain[IR_CNEWI])))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
247 if (!J->loopref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
248 sink_mark_snap(J, &J->cur.snap[J->cur.nsnap-1]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
249 sink_mark_ins(J);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
250 if (J->loopref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
251 sink_remark_phi(J);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
252 sink_sweep_ins(J);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
253 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
254 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
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255
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
256 #undef IR
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
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257
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
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258 #endif