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annotate third_party/luajit/src/lj_target_x86.h @ 279:b3b547563ec7

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Add Google connector service and agent wiki Implement the C/Seobeo Google Drive and Gmail connector with encrypted OAuth storage, Zenbu authentication, browser testing, AI tool discovery, chunked HTTP decoding, and Bazel coverage. Consolidate repository guidance into progressive wiki documentation and enforce arena-first allocation for new first-party C code. Co-authored-by: Copilot <[email protected]> Copilot-Session: 84c338fd-0939-4bb3-b7f3-1062eb213e5d
author MrJuneJune <me@mrjunejune.com>
date Mon, 17 Aug 2026 22:22:36 -0700
parents 94705b5986b3
children
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178
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1 /*
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2 ** Definitions for x86 and x64 CPUs.
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3 ** Copyright (C) 2005-2023 Mike Pall. See Copyright Notice in luajit.h
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4 */
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5
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6 #ifndef _LJ_TARGET_X86_H
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7 #define _LJ_TARGET_X86_H
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8
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9 /* -- Registers IDs ------------------------------------------------------- */
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10
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11 #if LJ_64
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12 #define GPRDEF(_) \
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13 _(EAX) _(ECX) _(EDX) _(EBX) _(ESP) _(EBP) _(ESI) _(EDI) \
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14 _(R8D) _(R9D) _(R10D) _(R11D) _(R12D) _(R13D) _(R14D) _(R15D)
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15 #define FPRDEF(_) \
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16 _(XMM0) _(XMM1) _(XMM2) _(XMM3) _(XMM4) _(XMM5) _(XMM6) _(XMM7) \
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17 _(XMM8) _(XMM9) _(XMM10) _(XMM11) _(XMM12) _(XMM13) _(XMM14) _(XMM15)
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18 #else
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19 #define GPRDEF(_) \
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20 _(EAX) _(ECX) _(EDX) _(EBX) _(ESP) _(EBP) _(ESI) _(EDI)
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21 #define FPRDEF(_) \
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22 _(XMM0) _(XMM1) _(XMM2) _(XMM3) _(XMM4) _(XMM5) _(XMM6) _(XMM7)
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23 #endif
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24 #define VRIDDEF(_) \
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25 _(MRM) _(RIP)
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26
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27 #define RIDENUM(name) RID_##name,
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28
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29 enum {
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30 GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */
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31 FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */
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32 RID_MAX,
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33 RID_MRM = RID_MAX, /* Pseudo-id for ModRM operand. */
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34 RID_RIP = RID_MAX+5, /* Pseudo-id for RIP (x64 only), rm bits = 5. */
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35
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36 /* Calling conventions. */
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37 RID_SP = RID_ESP,
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38 RID_RET = RID_EAX,
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39 #if LJ_64
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40 RID_FPRET = RID_XMM0,
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41 #endif
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42 RID_RETLO = RID_EAX,
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43 RID_RETHI = RID_EDX,
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44
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45 /* These definitions must match with the *.dasc file(s): */
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46 RID_BASE = RID_EDX, /* Interpreter BASE. */
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47 #if LJ_64 && !LJ_ABI_WIN
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48 RID_LPC = RID_EBX, /* Interpreter PC. */
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49 RID_DISPATCH = RID_R14D, /* Interpreter DISPATCH table. */
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50 #else
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51 RID_LPC = RID_ESI, /* Interpreter PC. */
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52 RID_DISPATCH = RID_EBX, /* Interpreter DISPATCH table. */
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53 #endif
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54
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55 /* Register ranges [min, max) and number of registers. */
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56 RID_MIN_GPR = RID_EAX,
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57 RID_MIN_FPR = RID_XMM0,
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58 RID_MAX_GPR = RID_MIN_FPR,
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59 RID_MAX_FPR = RID_MAX,
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60 RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR,
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61 RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR,
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62 };
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63
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64 /* -- Register sets ------------------------------------------------------- */
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65
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66 /* Make use of all registers, except the stack pointer (and maybe DISPATCH). */
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67 #define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) \
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68 - RID2RSET(RID_ESP) \
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69 - LJ_GC64*RID2RSET(RID_DISPATCH))
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70 #define RSET_FPR (RSET_RANGE(RID_MIN_FPR, RID_MAX_FPR))
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71 #define RSET_ALL (RSET_GPR|RSET_FPR)
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72 #define RSET_INIT RSET_ALL
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73
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74 #if LJ_64
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75 /* Note: this requires the use of FORCE_REX! */
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76 #define RSET_GPR8 RSET_GPR
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77 #else
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78 #define RSET_GPR8 (RSET_RANGE(RID_EAX, RID_EBX+1))
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79 #endif
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80
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81 /* ABI-specific register sets. */
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82 #define RSET_ACD (RID2RSET(RID_EAX)|RID2RSET(RID_ECX)|RID2RSET(RID_EDX))
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83 #if LJ_64
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84 #if LJ_ABI_WIN
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85 /* Windows x64 ABI. */
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86 #define RSET_SCRATCH \
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87 (RSET_ACD|RSET_RANGE(RID_R8D, RID_R11D+1)|RSET_RANGE(RID_XMM0, RID_XMM5+1))
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88 #define REGARG_GPRS \
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89 (RID_ECX|((RID_EDX|((RID_R8D|(RID_R9D<<5))<<5))<<5))
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90 #define REGARG_NUMGPR 4
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91 #define REGARG_NUMFPR 4
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92 #define REGARG_FIRSTFPR RID_XMM0
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93 #define REGARG_LASTFPR RID_XMM3
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94 #define STACKARG_OFS (4*8)
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95 #else
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96 /* The rest of the civilized x64 world has a common ABI. */
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97 #define RSET_SCRATCH \
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98 (RSET_ACD|RSET_RANGE(RID_ESI, RID_R11D+1)|RSET_FPR)
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99 #define REGARG_GPRS \
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100 (RID_EDI|((RID_ESI|((RID_EDX|((RID_ECX|((RID_R8D|(RID_R9D \
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101 <<5))<<5))<<5))<<5))<<5))
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102 #define REGARG_NUMGPR 6
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103 #define REGARG_NUMFPR 8
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104 #define REGARG_FIRSTFPR RID_XMM0
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105 #define REGARG_LASTFPR RID_XMM7
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106 #define STACKARG_OFS 0
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107 #endif
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108 #else
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109 /* Common x86 ABI. */
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110 #define RSET_SCRATCH (RSET_ACD|RSET_FPR)
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111 #define REGARG_GPRS (RID_ECX|(RID_EDX<<5)) /* Fastcall only. */
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112 #define REGARG_NUMGPR 2 /* Fastcall only. */
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113 #define REGARG_NUMFPR 0
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114 #define STACKARG_OFS 0
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115 #endif
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116
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117 #if LJ_64
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118 /* Prefer the low 8 regs of each type to reduce REX prefixes. */
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119 #undef rset_picktop
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120 #define rset_picktop(rs) (lj_fls(lj_bswap(rs)) ^ 0x18)
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121 #endif
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122
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123 /* -- Spill slots --------------------------------------------------------- */
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124
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125 /* Spill slots are 32 bit wide. An even/odd pair is used for FPRs.
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126 **
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127 ** SPS_FIXED: Available fixed spill slots in interpreter frame.
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128 ** This definition must match with the *.dasc file(s).
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129 **
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130 ** SPS_FIRST: First spill slot for general use. Reserve min. two 32 bit slots.
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131 */
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132 #if LJ_64
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133 #if LJ_ABI_WIN
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134 #define SPS_FIXED (4*2)
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135 #define SPS_FIRST (4*2) /* Don't use callee register save area. */
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136 #else
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137 #if LJ_GC64
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138 #define SPS_FIXED 2
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139 #else
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140 #define SPS_FIXED 4
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141 #endif
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142 #define SPS_FIRST 2
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143 #endif
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144 #else
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145 #define SPS_FIXED 6
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146 #define SPS_FIRST 2
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147 #endif
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148
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149 #define SPOFS_TMP 0
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150
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151 #define sps_scale(slot) (4 * (int32_t)(slot))
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152 #define sps_align(slot) (((slot) - SPS_FIXED + 3) & ~3)
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153
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154 /* -- Exit state ---------------------------------------------------------- */
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155
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156 /* This definition must match with the *.dasc file(s). */
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157 typedef struct {
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158 lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */
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159 intptr_t gpr[RID_NUM_GPR]; /* General-purpose registers. */
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160 int32_t spill[256]; /* Spill slots. */
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161 } ExitState;
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162
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163 /* Limited by the range of a short fwd jump (127): (2+2)*(32-1)-2 = 122. */
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164 #define EXITSTUB_SPACING (2+2)
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165 #define EXITSTUBS_PER_GROUP 32
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166
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167 #define EXITTRACE_VMSTATE 1 /* g->vmstate has traceno on exit. */
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168
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169 /* -- x86 ModRM operand encoding ------------------------------------------ */
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170
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171 typedef enum {
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172 XM_OFS0 = 0x00, XM_OFS8 = 0x40, XM_OFS32 = 0x80, XM_REG = 0xc0,
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173 XM_SCALE1 = 0x00, XM_SCALE2 = 0x40, XM_SCALE4 = 0x80, XM_SCALE8 = 0xc0,
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174 XM_MASK = 0xc0
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175 } x86Mode;
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176
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177 /* Structure to hold variable ModRM operand. */
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178 typedef struct {
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179 int32_t ofs; /* Offset. */
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180 uint8_t base; /* Base register or RID_NONE. */
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181 uint8_t idx; /* Index register or RID_NONE. */
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182 uint8_t scale; /* Index scale (XM_SCALE1 .. XM_SCALE8). */
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183 } x86ModRM;
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184
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185 /* -- Opcodes ------------------------------------------------------------- */
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186
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187 /* Macros to construct variable-length x86 opcodes. -(len+1) is in LSB. */
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188 #define XO_(o) ((uint32_t)(0x0000fe + (0x##o<<24)))
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189 #define XO_FPU(a,b) ((uint32_t)(0x00fd + (0x##a<<16)+(0x##b<<24)))
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190 #define XO_0f(o) ((uint32_t)(0x0f00fd + (0x##o<<24)))
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191 #define XO_66(o) ((uint32_t)(0x6600fd + (0x##o<<24)))
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192 #define XO_660f(o) ((uint32_t)(0x0f66fc + (0x##o<<24)))
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193 #define XO_f20f(o) ((uint32_t)(0x0ff2fc + (0x##o<<24)))
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194 #define XO_f30f(o) ((uint32_t)(0x0ff3fc + (0x##o<<24)))
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195
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196 #define XV_660f38(o) ((uint32_t)(0x79e2c4 + (0x##o<<24)))
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197 #define XV_f20f38(o) ((uint32_t)(0x7be2c4 + (0x##o<<24)))
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198 #define XV_f20f3a(o) ((uint32_t)(0x7be3c4 + (0x##o<<24)))
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199 #define XV_f30f38(o) ((uint32_t)(0x7ae2c4 + (0x##o<<24)))
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200
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201 /* This list of x86 opcodes is not intended to be complete. Opcodes are only
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202 ** included when needed. Take a look at DynASM or jit.dis_x86 to see the
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203 ** whole mess.
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204 */
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205 typedef enum {
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206 /* Fixed length opcodes. XI_* prefix. */
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207 XI_O16 = 0x66,
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208 XI_NOP = 0x90,
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209 XI_XCHGa = 0x90,
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210 XI_CALL = 0xe8,
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211 XI_JMP = 0xe9,
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212 XI_JMPs = 0xeb,
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213 XI_PUSH = 0x50, /* Really 50+r. */
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214 XI_JCCs = 0x70, /* Really 7x. */
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215 XI_JCCn = 0x80, /* Really 0f8x. */
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216 XI_LEA = 0x8d,
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217 XI_MOVrib = 0xb0, /* Really b0+r. */
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218 XI_MOVri = 0xb8, /* Really b8+r. */
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219 XI_ARITHib = 0x80,
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220 XI_ARITHi = 0x81,
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221 XI_ARITHi8 = 0x83,
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222 XI_PUSHi8 = 0x6a,
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223 XI_TESTb = 0x84,
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224 XI_TEST = 0x85,
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225 XI_INT3 = 0xcc,
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226 XI_MOVmi = 0xc7,
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227 XI_GROUP5 = 0xff,
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228
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229 /* Note: little-endian byte-order! */
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230 XI_FLDZ = 0xeed9,
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231 XI_FLD1 = 0xe8d9,
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232 XI_FDUP = 0xc0d9, /* Really fld st0. */
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233 XI_FPOP = 0xd8dd, /* Really fstp st0. */
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234 XI_FPOP1 = 0xd9dd, /* Really fstp st1. */
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235 XI_FRNDINT = 0xfcd9,
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236 XI_FSCALE = 0xfdd9,
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237 XI_FYL2X = 0xf1d9,
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238
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239 /* VEX-encoded instructions. XV_* prefix. */
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240 XV_RORX = XV_f20f3a(f0),
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241 XV_SARX = XV_f30f38(f7),
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242 XV_SHLX = XV_660f38(f7),
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243 XV_SHRX = XV_f20f38(f7),
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244
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diff changeset
245 /* Variable-length opcodes. XO_* prefix. */
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parents:
diff changeset
246 XO_OR = XO_(0b),
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MrJuneJune <me@mrjunejune.com>
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diff changeset
247 XO_MOV = XO_(8b),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
248 XO_MOVto = XO_(89),
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MrJuneJune <me@mrjunejune.com>
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diff changeset
249 XO_MOVtow = XO_66(89),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
250 XO_MOVtob = XO_(88),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
251 XO_MOVmi = XO_(c7),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
252 XO_MOVmib = XO_(c6),
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parents:
diff changeset
253 XO_LEA = XO_(8d),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
254 XO_ARITHib = XO_(80),
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parents:
diff changeset
255 XO_ARITHi = XO_(81),
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MrJuneJune <me@mrjunejune.com>
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diff changeset
256 XO_ARITHi8 = XO_(83),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
257 XO_ARITHiw8 = XO_66(83),
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diff changeset
258 XO_SHIFTi = XO_(c1),
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parents:
diff changeset
259 XO_SHIFT1 = XO_(d1),
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parents:
diff changeset
260 XO_SHIFTcl = XO_(d3),
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parents:
diff changeset
261 XO_IMUL = XO_0f(af),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
262 XO_IMULi = XO_(69),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
263 XO_IMULi8 = XO_(6b),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
264 XO_CMP = XO_(3b),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
265 XO_TESTb = XO_(84),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
266 XO_TEST = XO_(85),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
267 XO_GROUP3b = XO_(f6),
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parents:
diff changeset
268 XO_GROUP3 = XO_(f7),
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parents:
diff changeset
269 XO_GROUP5b = XO_(fe),
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diff changeset
270 XO_GROUP5 = XO_(ff),
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diff changeset
271 XO_MOVZXb = XO_0f(b6),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
272 XO_MOVZXw = XO_0f(b7),
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diff changeset
273 XO_MOVSXb = XO_0f(be),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
274 XO_MOVSXw = XO_0f(bf),
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parents:
diff changeset
275 XO_MOVSXd = XO_(63),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
276 XO_BSWAP = XO_0f(c8),
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parents:
diff changeset
277 XO_CMOV = XO_0f(40),
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diff changeset
278
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diff changeset
279 XO_MOVSD = XO_f20f(10),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
280 XO_MOVSDto = XO_f20f(11),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
281 XO_MOVSS = XO_f30f(10),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
282 XO_MOVSSto = XO_f30f(11),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
283 XO_MOVLPD = XO_660f(12),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
284 XO_MOVAPS = XO_0f(28),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
285 XO_XORPS = XO_0f(57),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
286 XO_ANDPS = XO_0f(54),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
287 XO_ADDSD = XO_f20f(58),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
288 XO_SUBSD = XO_f20f(5c),
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parents:
diff changeset
289 XO_MULSD = XO_f20f(59),
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parents:
diff changeset
290 XO_DIVSD = XO_f20f(5e),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
291 XO_SQRTSD = XO_f20f(51),
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
292 XO_MINSD = XO_f20f(5d),
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diff changeset
293 XO_MAXSD = XO_f20f(5f),
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diff changeset
294 XO_ROUNDSD = 0x0b3a0ffc, /* Really 66 0f 3a 0b. See asm_fpmath. */
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diff changeset
295 XO_UCOMISD = XO_660f(2e),
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diff changeset
296 XO_CVTSI2SD = XO_f20f(2a),
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diff changeset
297 XO_CVTTSD2SI= XO_f20f(2c),
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diff changeset
298 XO_CVTSI2SS = XO_f30f(2a),
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diff changeset
299 XO_CVTTSS2SI= XO_f30f(2c),
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diff changeset
300 XO_CVTSS2SD = XO_f30f(5a),
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diff changeset
301 XO_CVTSD2SS = XO_f20f(5a),
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diff changeset
302 XO_ADDSS = XO_f30f(58),
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303 XO_MOVD = XO_660f(6e),
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diff changeset
304 XO_MOVDto = XO_660f(7e),
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diff changeset
305
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diff changeset
306 XO_FLDd = XO_(d9), XOg_FLDd = 0,
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diff changeset
307 XO_FLDq = XO_(dd), XOg_FLDq = 0,
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diff changeset
308 XO_FILDd = XO_(db), XOg_FILDd = 0,
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diff changeset
309 XO_FILDq = XO_(df), XOg_FILDq = 5,
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diff changeset
310 XO_FSTPd = XO_(d9), XOg_FSTPd = 3,
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diff changeset
311 XO_FSTPq = XO_(dd), XOg_FSTPq = 3,
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diff changeset
312 XO_FISTPq = XO_(df), XOg_FISTPq = 7,
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diff changeset
313 XO_FISTTPq = XO_(dd), XOg_FISTTPq = 1,
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diff changeset
314 XO_FADDq = XO_(dc), XOg_FADDq = 0,
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diff changeset
315 XO_FLDCW = XO_(d9), XOg_FLDCW = 5,
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diff changeset
316 XO_FNSTCW = XO_(d9), XOg_FNSTCW = 7
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diff changeset
317 } x86Op;
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parents:
diff changeset
318
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diff changeset
319 /* x86 opcode groups. */
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parents:
diff changeset
320 typedef uint32_t x86Group;
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321
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diff changeset
322 #define XG_(i8, i, g) ((x86Group)(((i8) << 16) + ((i) << 8) + (g)))
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parents:
diff changeset
323 #define XG_ARITHi(g) XG_(XI_ARITHi8, XI_ARITHi, g)
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diff changeset
324 #define XG_TOXOi(xg) ((x86Op)(0x000000fe + (((xg)<<16) & 0xff000000)))
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diff changeset
325 #define XG_TOXOi8(xg) ((x86Op)(0x000000fe + (((xg)<<8) & 0xff000000)))
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parents:
diff changeset
326
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parents:
diff changeset
327 #define XO_ARITH(a) ((x86Op)(0x030000fe + ((a)<<27)))
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
328 #define XO_ARITHw(a) ((x86Op)(0x036600fd + ((a)<<27)))
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parents:
diff changeset
329
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
330 typedef enum {
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diff changeset
331 XOg_ADD, XOg_OR, XOg_ADC, XOg_SBB, XOg_AND, XOg_SUB, XOg_XOR, XOg_CMP,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
332 XOg_X_IMUL
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
333 } x86Arith;
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
334
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
335 typedef enum {
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diff changeset
336 XOg_ROL, XOg_ROR, XOg_RCL, XOg_RCR, XOg_SHL, XOg_SHR, XOg_SAL, XOg_SAR
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
337 } x86Shift;
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
338
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
339 typedef enum {
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parents:
diff changeset
340 XOg_TEST, XOg_TEST_, XOg_NOT, XOg_NEG, XOg_MUL, XOg_IMUL, XOg_DIV, XOg_IDIV
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
341 } x86Group3;
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
342
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
343 typedef enum {
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diff changeset
344 XOg_INC, XOg_DEC, XOg_CALL, XOg_CALLfar, XOg_JMP, XOg_JMPfar, XOg_PUSH
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
345 } x86Group5;
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
346
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
347 /* x86 condition codes. */
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
348 typedef enum {
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parents:
diff changeset
349 CC_O, CC_NO, CC_B, CC_NB, CC_E, CC_NE, CC_BE, CC_NBE,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
350 CC_S, CC_NS, CC_P, CC_NP, CC_L, CC_NL, CC_LE, CC_NLE,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
351 CC_C = CC_B, CC_NAE = CC_C, CC_NC = CC_NB, CC_AE = CC_NB,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
352 CC_Z = CC_E, CC_NZ = CC_NE, CC_NA = CC_BE, CC_A = CC_NBE,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
353 CC_PE = CC_P, CC_PO = CC_NP, CC_NGE = CC_L, CC_GE = CC_NL,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
354 CC_NG = CC_LE, CC_G = CC_NLE
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
355 } x86CC;
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
356
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
357 #endif