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annotate third_party/luajit/src/lj_target_arm.h @ 279:b3b547563ec7

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Add Google connector service and agent wiki Implement the C/Seobeo Google Drive and Gmail connector with encrypted OAuth storage, Zenbu authentication, browser testing, AI tool discovery, chunked HTTP decoding, and Bazel coverage. Consolidate repository guidance into progressive wiki documentation and enforce arena-first allocation for new first-party C code. Co-authored-by: Copilot <[email protected]> Copilot-Session: 84c338fd-0939-4bb3-b7f3-1062eb213e5d
author MrJuneJune <me@mrjunejune.com>
date Mon, 17 Aug 2026 22:22:36 -0700
parents 94705b5986b3
children
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178
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1 /*
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2 ** Definitions for ARM CPUs.
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3 ** Copyright (C) 2005-2023 Mike Pall. See Copyright Notice in luajit.h
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4 */
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5
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6 #ifndef _LJ_TARGET_ARM_H
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7 #define _LJ_TARGET_ARM_H
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8
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9 /* -- Registers IDs ------------------------------------------------------- */
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10
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11 #define GPRDEF(_) \
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12 _(R0) _(R1) _(R2) _(R3) _(R4) _(R5) _(R6) _(R7) \
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13 _(R8) _(R9) _(R10) _(R11) _(R12) _(SP) _(LR) _(PC)
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14 #if LJ_SOFTFP
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15 #define FPRDEF(_)
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16 #else
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17 #define FPRDEF(_) \
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18 _(D0) _(D1) _(D2) _(D3) _(D4) _(D5) _(D6) _(D7) \
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19 _(D8) _(D9) _(D10) _(D11) _(D12) _(D13) _(D14) _(D15)
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20 #endif
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21 #define VRIDDEF(_)
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22
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23 #define RIDENUM(name) RID_##name,
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24
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25 enum {
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26 GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */
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27 FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */
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28 RID_MAX,
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29 RID_TMP = RID_LR,
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30
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31 /* Calling conventions. */
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32 RID_RET = RID_R0,
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33 RID_RETLO = RID_R0,
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34 RID_RETHI = RID_R1,
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35 #if LJ_SOFTFP
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36 RID_FPRET = RID_R0,
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37 #else
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38 RID_FPRET = RID_D0,
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39 #endif
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40
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41 /* These definitions must match with the *.dasc file(s): */
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42 RID_BASE = RID_R9, /* Interpreter BASE. */
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43 RID_LPC = RID_R6, /* Interpreter PC. */
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44 RID_DISPATCH = RID_R7, /* Interpreter DISPATCH table. */
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45 RID_LREG = RID_R8, /* Interpreter L. */
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46
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47 /* Register ranges [min, max) and number of registers. */
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48 RID_MIN_GPR = RID_R0,
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49 RID_MAX_GPR = RID_PC+1,
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50 RID_MIN_FPR = RID_MAX_GPR,
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51 #if LJ_SOFTFP
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52 RID_MAX_FPR = RID_MIN_FPR,
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53 #else
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54 RID_MAX_FPR = RID_D15+1,
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55 #endif
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56 RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR,
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57 RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR
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58 };
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59
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60 #define RID_NUM_KREF RID_NUM_GPR
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61 #define RID_MIN_KREF RID_R0
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62
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63 /* -- Register sets ------------------------------------------------------- */
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64
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65 /* Make use of all registers, except sp, lr and pc. */
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66 #define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_R12+1))
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67 #define RSET_GPREVEN \
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68 (RID2RSET(RID_R0)|RID2RSET(RID_R2)|RID2RSET(RID_R4)|RID2RSET(RID_R6)| \
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69 RID2RSET(RID_R8)|RID2RSET(RID_R10))
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70 #define RSET_GPRODD \
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71 (RID2RSET(RID_R1)|RID2RSET(RID_R3)|RID2RSET(RID_R5)|RID2RSET(RID_R7)| \
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72 RID2RSET(RID_R9)|RID2RSET(RID_R11))
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73 #if LJ_SOFTFP
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74 #define RSET_FPR 0
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75 #else
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76 #define RSET_FPR (RSET_RANGE(RID_MIN_FPR, RID_MAX_FPR))
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77 #endif
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78 #define RSET_ALL (RSET_GPR|RSET_FPR)
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79 #define RSET_INIT RSET_ALL
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80
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81 /* ABI-specific register sets. lr is an implicit scratch register. */
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82 #define RSET_SCRATCH_GPR_ (RSET_RANGE(RID_R0, RID_R3+1)|RID2RSET(RID_R12))
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83 #ifdef __APPLE__
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84 #define RSET_SCRATCH_GPR (RSET_SCRATCH_GPR_|RID2RSET(RID_R9))
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85 #else
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86 #define RSET_SCRATCH_GPR RSET_SCRATCH_GPR_
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87 #endif
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88 #if LJ_SOFTFP
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89 #define RSET_SCRATCH_FPR 0
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90 #else
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91 #define RSET_SCRATCH_FPR (RSET_RANGE(RID_D0, RID_D7+1))
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92 #endif
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93 #define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR)
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94 #define REGARG_FIRSTGPR RID_R0
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95 #define REGARG_LASTGPR RID_R3
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96 #define REGARG_NUMGPR 4
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97 #if LJ_ABI_SOFTFP
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98 #define REGARG_FIRSTFPR 0
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99 #define REGARG_LASTFPR 0
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100 #define REGARG_NUMFPR 0
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101 #else
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102 #define REGARG_FIRSTFPR RID_D0
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103 #define REGARG_LASTFPR RID_D7
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104 #define REGARG_NUMFPR 8
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105 #endif
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106
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107 /* -- Spill slots --------------------------------------------------------- */
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108
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109 /* Spill slots are 32 bit wide. An even/odd pair is used for FPRs.
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110 **
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111 ** SPS_FIXED: Available fixed spill slots in interpreter frame.
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112 ** This definition must match with the *.dasc file(s).
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113 **
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114 ** SPS_FIRST: First spill slot for general use. Reserve min. two 32 bit slots.
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115 */
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116 #define SPS_FIXED 2
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117 #define SPS_FIRST 2
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118
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119 #define SPOFS_TMP 0
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120
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121 #define sps_scale(slot) (4 * (int32_t)(slot))
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122 #define sps_align(slot) (((slot) - SPS_FIXED + 1) & ~1)
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123
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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124 /* -- Exit state ---------------------------------------------------------- */
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diff changeset
125
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diff changeset
126 /* This definition must match with the *.dasc file(s). */
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diff changeset
127 typedef struct {
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128 #if !LJ_SOFTFP
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129 lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */
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diff changeset
130 #endif
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131 int32_t gpr[RID_NUM_GPR]; /* General-purpose registers. */
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132 int32_t spill[256]; /* Spill slots. */
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133 } ExitState;
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134
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diff changeset
135 /* PC after instruction that caused an exit. Used to find the trace number. */
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diff changeset
136 #define EXITSTATE_PCREG RID_PC
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diff changeset
137 /* Highest exit + 1 indicates stack check. */
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MrJuneJune <me@mrjunejune.com>
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diff changeset
138 #define EXITSTATE_CHECKEXIT 1
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139
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diff changeset
140 #define EXITSTUB_SPACING 4
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MrJuneJune <me@mrjunejune.com>
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diff changeset
141 #define EXITSTUBS_PER_GROUP 32
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diff changeset
142
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
143 /* -- Instructions -------------------------------------------------------- */
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diff changeset
144
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diff changeset
145 /* Instruction fields. */
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146 #define ARMF_CC(ai, cc) (((ai) ^ ARMI_CCAL) | ((cc) << 28))
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parents:
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147 #define ARMF_N(r) ((r) << 16)
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148 #define ARMF_D(r) ((r) << 12)
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149 #define ARMF_S(r) ((r) << 8)
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diff changeset
150 #define ARMF_M(r) (r)
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151 #define ARMF_SH(sh, n) (((sh) << 5) | ((n) << 7))
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152 #define ARMF_RSH(sh, r) (0x10 | ((sh) << 5) | ARMF_S(r))
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153
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
154 typedef enum ARMIns {
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diff changeset
155 ARMI_CCAL = 0xe0000000,
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MrJuneJune <me@mrjunejune.com>
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diff changeset
156 ARMI_S = 0x000100000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
157 ARMI_K12 = 0x02000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
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diff changeset
158 ARMI_KNEG = 0x00200000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
159 ARMI_LS_W = 0x00200000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
160 ARMI_LS_U = 0x00800000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
161 ARMI_LS_P = 0x01000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
162 ARMI_LS_R = 0x02000000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
163 ARMI_LSX_I = 0x00400000,
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diff changeset
164
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
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diff changeset
165 ARMI_AND = 0xe0000000,
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MrJuneJune <me@mrjunejune.com>
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diff changeset
166 ARMI_EOR = 0xe0200000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
167 ARMI_SUB = 0xe0400000,
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MrJuneJune <me@mrjunejune.com>
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diff changeset
168 ARMI_RSB = 0xe0600000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
169 ARMI_ADD = 0xe0800000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
170 ARMI_ADC = 0xe0a00000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
171 ARMI_SBC = 0xe0c00000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
172 ARMI_RSC = 0xe0e00000,
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diff changeset
173 ARMI_TST = 0xe1100000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
174 ARMI_TEQ = 0xe1300000,
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MrJuneJune <me@mrjunejune.com>
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diff changeset
175 ARMI_CMP = 0xe1500000,
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MrJuneJune <me@mrjunejune.com>
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diff changeset
176 ARMI_CMN = 0xe1700000,
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MrJuneJune <me@mrjunejune.com>
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diff changeset
177 ARMI_ORR = 0xe1800000,
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MrJuneJune <me@mrjunejune.com>
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diff changeset
178 ARMI_MOV = 0xe1a00000,
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diff changeset
179 ARMI_BIC = 0xe1c00000,
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parents:
diff changeset
180 ARMI_MVN = 0xe1e00000,
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parents:
diff changeset
181
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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diff changeset
182 ARMI_NOP = 0xe1a00000,
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parents:
diff changeset
183
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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diff changeset
184 ARMI_MUL = 0xe0000090,
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MrJuneJune <me@mrjunejune.com>
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diff changeset
185 ARMI_SMULL = 0xe0c00090,
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parents:
diff changeset
186
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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diff changeset
187 ARMI_LDR = 0xe4100000,
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MrJuneJune <me@mrjunejune.com>
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diff changeset
188 ARMI_LDRB = 0xe4500000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
189 ARMI_LDRH = 0xe01000b0,
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parents:
diff changeset
190 ARMI_LDRSB = 0xe01000d0,
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parents:
diff changeset
191 ARMI_LDRSH = 0xe01000f0,
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parents:
diff changeset
192 ARMI_LDRD = 0xe00000d0,
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parents:
diff changeset
193 ARMI_STR = 0xe4000000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
194 ARMI_STRB = 0xe4400000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
195 ARMI_STRH = 0xe00000b0,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
196 ARMI_STRD = 0xe00000f0,
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parents:
diff changeset
197 ARMI_PUSH = 0xe92d0000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
198
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
199 ARMI_B = 0xea000000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
200 ARMI_BL = 0xeb000000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
201 ARMI_BLX = 0xfa000000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
202 ARMI_BLXr = 0xe12fff30,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
203
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
204 /* ARMv6 */
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
205 ARMI_REV = 0xe6bf0f30,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
206 ARMI_SXTB = 0xe6af0070,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
207 ARMI_SXTH = 0xe6bf0070,
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parents:
diff changeset
208 ARMI_UXTB = 0xe6ef0070,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
209 ARMI_UXTH = 0xe6ff0070,
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parents:
diff changeset
210
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
211 /* ARMv6T2 */
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
212 ARMI_MOVW = 0xe3000000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
213 ARMI_MOVT = 0xe3400000,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
214 ARMI_BFI = 0xe7c00010,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
215
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
216 /* VFP */
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
217 ARMI_VMOV_D = 0xeeb00b40,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
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parents:
diff changeset
218 ARMI_VMOV_S = 0xeeb00a40,
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parents:
diff changeset
219 ARMI_VMOVI_D = 0xeeb00b00,
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parents:
diff changeset
220
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
221 ARMI_VMOV_R_S = 0xee100a10,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
222 ARMI_VMOV_S_R = 0xee000a10,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
223 ARMI_VMOV_RR_D = 0xec500b10,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
224 ARMI_VMOV_D_RR = 0xec400b10,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
225
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
226 ARMI_VADD_D = 0xee300b00,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
227 ARMI_VSUB_D = 0xee300b40,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
228 ARMI_VMUL_D = 0xee200b00,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
229 ARMI_VMLA_D = 0xee000b00,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
230 ARMI_VMLS_D = 0xee000b40,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
231 ARMI_VNMLS_D = 0xee100b00,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
232 ARMI_VDIV_D = 0xee800b00,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
233
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
234 ARMI_VABS_D = 0xeeb00bc0,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
235 ARMI_VNEG_D = 0xeeb10b40,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
236 ARMI_VSQRT_D = 0xeeb10bc0,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
237
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
238 ARMI_VCMP_D = 0xeeb40b40,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
239 ARMI_VCMPZ_D = 0xeeb50b40,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
240
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
241 ARMI_VMRS = 0xeef1fa10,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
242
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
243 ARMI_VCVT_S32_F32 = 0xeebd0ac0,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
244 ARMI_VCVT_S32_F64 = 0xeebd0bc0,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
245 ARMI_VCVT_U32_F32 = 0xeebc0ac0,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
246 ARMI_VCVT_U32_F64 = 0xeebc0bc0,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
247 ARMI_VCVT_F32_S32 = 0xeeb80ac0,
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
248 ARMI_VCVT_F64_S32 = 0xeeb80bc0,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
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249 ARMI_VCVT_F32_U32 = 0xeeb80a40,
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250 ARMI_VCVT_F64_U32 = 0xeeb80b40,
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251 ARMI_VCVT_F32_F64 = 0xeeb70bc0,
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252 ARMI_VCVT_F64_F32 = 0xeeb70ac0,
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253
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254 ARMI_VLDR_S = 0xed100a00,
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255 ARMI_VLDR_D = 0xed100b00,
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256 ARMI_VSTR_S = 0xed000a00,
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257 ARMI_VSTR_D = 0xed000b00,
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258 } ARMIns;
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259
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260 typedef enum ARMShift {
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261 ARMSH_LSL, ARMSH_LSR, ARMSH_ASR, ARMSH_ROR
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262 } ARMShift;
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263
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264 /* ARM condition codes. */
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265 typedef enum ARMCC {
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266 CC_EQ, CC_NE, CC_CS, CC_CC, CC_MI, CC_PL, CC_VS, CC_VC,
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267 CC_HI, CC_LS, CC_GE, CC_LT, CC_GT, CC_LE, CC_AL,
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268 CC_HS = CC_CS, CC_LO = CC_CC
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269 } ARMCC;
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270
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271 #endif