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annotate third_party/luajit/src/lj_target.h @ 279:b3b547563ec7

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Add Google connector service and agent wiki Implement the C/Seobeo Google Drive and Gmail connector with encrypted OAuth storage, Zenbu authentication, browser testing, AI tool discovery, chunked HTTP decoding, and Bazel coverage. Consolidate repository guidance into progressive wiki documentation and enforce arena-first allocation for new first-party C code. Co-authored-by: Copilot <[email protected]> Copilot-Session: 84c338fd-0939-4bb3-b7f3-1062eb213e5d
author MrJuneJune <me@mrjunejune.com>
date Mon, 17 Aug 2026 22:22:36 -0700
parents 94705b5986b3
children
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178
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1 /*
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2 ** Definitions for target CPU.
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3 ** Copyright (C) 2005-2023 Mike Pall. See Copyright Notice in luajit.h
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4 */
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5
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6 #ifndef _LJ_TARGET_H
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7 #define _LJ_TARGET_H
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8
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9 #include "lj_def.h"
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10 #include "lj_arch.h"
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11
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12 /* -- Registers and spill slots ------------------------------------------- */
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13
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14 /* Register type (uint8_t in ir->r). */
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15 typedef uint32_t Reg;
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16
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17 /* The hi-bit is NOT set for an allocated register. This means the value
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18 ** can be directly used without masking. The hi-bit is set for a register
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19 ** allocation hint or for RID_INIT, RID_SINK or RID_SUNK.
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20 */
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21 #define RID_NONE 0x80
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22 #define RID_MASK 0x7f
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23 #define RID_INIT (RID_NONE|RID_MASK)
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24 #define RID_SINK (RID_INIT-1)
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25 #define RID_SUNK (RID_INIT-2)
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26
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27 #define ra_noreg(r) ((r) & RID_NONE)
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28 #define ra_hasreg(r) (!((r) & RID_NONE))
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29
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30 /* The ra_hashint() macro assumes a previous test for ra_noreg(). */
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31 #define ra_hashint(r) ((r) < RID_SUNK)
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32 #define ra_gethint(r) ((Reg)((r) & RID_MASK))
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33 #define ra_sethint(rr, r) rr = (uint8_t)((r)|RID_NONE)
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34 #define ra_samehint(r1, r2) (ra_gethint((r1)^(r2)) == 0)
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35
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36 /* Spill slot 0 means no spill slot has been allocated. */
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37 #define SPS_NONE 0
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38
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39 #define ra_hasspill(s) ((s) != SPS_NONE)
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40
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41 /* Combined register and spill slot (uint16_t in ir->prev). */
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42 typedef uint32_t RegSP;
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43
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44 #define REGSP(r, s) ((r) + ((s) << 8))
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45 #define REGSP_HINT(r) ((r)|RID_NONE)
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46 #define REGSP_INIT REGSP(RID_INIT, 0)
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47
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48 #define regsp_reg(rs) ((rs) & 255)
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49 #define regsp_spill(rs) ((rs) >> 8)
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50 #define regsp_used(rs) \
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51 (((rs) & ~REGSP(RID_MASK, 0)) != REGSP(RID_NONE, 0))
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52
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53 /* -- Register sets ------------------------------------------------------- */
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54
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55 /* Bitset for registers. 32 registers suffice for most architectures.
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56 ** Note that one set holds bits for both GPRs and FPRs.
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57 */
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58 #if LJ_TARGET_PPC || LJ_TARGET_MIPS || LJ_TARGET_ARM64
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59 typedef uint64_t RegSet;
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60 #else
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61 typedef uint32_t RegSet;
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62 #endif
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63
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64 #define RID2RSET(r) (((RegSet)1) << (r))
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65 #define RSET_EMPTY ((RegSet)0)
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66 #define RSET_RANGE(lo, hi) ((RID2RSET((hi)-(lo))-1) << (lo))
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67
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68 #define rset_test(rs, r) ((int)((rs) >> (r)) & 1)
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69 #define rset_set(rs, r) (rs |= RID2RSET(r))
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70 #define rset_clear(rs, r) (rs &= ~RID2RSET(r))
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71 #define rset_exclude(rs, r) (rs & ~RID2RSET(r))
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72 #if LJ_TARGET_PPC || LJ_TARGET_MIPS || LJ_TARGET_ARM64
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73 #define rset_picktop(rs) ((Reg)(__builtin_clzll(rs)^63))
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74 #define rset_pickbot(rs) ((Reg)__builtin_ctzll(rs))
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75 #else
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76 #define rset_picktop(rs) ((Reg)lj_fls(rs))
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77 #define rset_pickbot(rs) ((Reg)lj_ffs(rs))
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78 #endif
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79
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80 /* -- Register allocation cost -------------------------------------------- */
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81
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82 /* The register allocation heuristic keeps track of the cost for allocating
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83 ** a specific register:
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84 **
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85 ** A free register (obviously) has a cost of 0 and a 1-bit in the free mask.
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86 **
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87 ** An already allocated register has the (non-zero) IR reference in the lowest
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88 ** bits and the result of a blended cost-model in the higher bits.
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89 **
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90 ** The allocator first checks the free mask for a hit. Otherwise an (unrolled)
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91 ** linear search for the minimum cost is used. The search doesn't need to
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92 ** keep track of the position of the minimum, which makes it very fast.
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93 ** The lowest bits of the minimum cost show the desired IR reference whose
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94 ** register is the one to evict.
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95 **
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96 ** Without the cost-model this degenerates to the standard heuristics for
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97 ** (reverse) linear-scan register allocation. Since code generation is done
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98 ** in reverse, a live interval extends from the last use to the first def.
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99 ** For an SSA IR the IR reference is the first (and only) def and thus
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100 ** trivially marks the end of the interval. The LSRA heuristics says to pick
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101 ** the register whose live interval has the furthest extent, i.e. the lowest
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102 ** IR reference in our case.
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103 **
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104 ** A cost-model should take into account other factors, like spill-cost and
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105 ** restore- or rematerialization-cost, which depend on the kind of instruction.
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106 ** E.g. constants have zero spill costs, variant instructions have higher
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107 ** costs than invariants and PHIs should preferably never be spilled.
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108 **
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109 ** Here's a first cut at simple, but effective blended cost-model for R-LSRA:
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110 ** - Due to careful design of the IR, constants already have lower IR
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111 ** references than invariants and invariants have lower IR references
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112 ** than variants.
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113 ** - The cost in the upper 16 bits is the sum of the IR reference and a
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114 ** weighted score. The score currently only takes into account whether
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115 ** the IRT_ISPHI bit is set in the instruction type.
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116 ** - The PHI weight is the minimum distance (in IR instructions) a PHI
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117 ** reference has to be further apart from a non-PHI reference to be spilled.
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118 ** - It should be a power of two (for speed) and must be between 2 and 32768.
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119 ** Good values for the PHI weight seem to be between 40 and 150.
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120 ** - Further study is required.
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121 */
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122 #define REGCOST_PHI_WEIGHT 64
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123
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124 /* Cost for allocating a specific register. */
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125 typedef uint32_t RegCost;
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126
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127 /* Note: assumes 16 bit IRRef1. */
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128 #define REGCOST(cost, ref) ((RegCost)(ref) + ((RegCost)(cost) << 16))
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129 #define regcost_ref(rc) ((IRRef1)(rc))
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130
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131 #define REGCOST_T(t) \
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132 ((RegCost)((t)&IRT_ISPHI) * (((RegCost)(REGCOST_PHI_WEIGHT)<<16)/IRT_ISPHI))
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133 #define REGCOST_REF_T(ref, t) (REGCOST((ref), (ref)) + REGCOST_T((t)))
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134
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135 /* -- Target-specific definitions ----------------------------------------- */
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136
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137 #if LJ_TARGET_X86ORX64
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138 #include "lj_target_x86.h"
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139 #elif LJ_TARGET_ARM
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140 #include "lj_target_arm.h"
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141 #elif LJ_TARGET_ARM64
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142 #include "lj_target_arm64.h"
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143 #elif LJ_TARGET_PPC
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144 #include "lj_target_ppc.h"
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145 #elif LJ_TARGET_MIPS
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146 #include "lj_target_mips.h"
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147 #else
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148 #error "Missing include for target CPU"
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149 #endif
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150
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151 #ifdef EXITSTUBS_PER_GROUP
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152 /* Return the address of an exit stub. */
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153 static LJ_AINLINE char *exitstub_addr_(char **group, uint32_t exitno)
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154 {
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155 lj_assertX(group[exitno / EXITSTUBS_PER_GROUP] != NULL,
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156 "exit stub group for exit %d uninitialized", exitno);
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157 return (char *)group[exitno / EXITSTUBS_PER_GROUP] +
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158 EXITSTUB_SPACING*(exitno % EXITSTUBS_PER_GROUP);
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159 }
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160 /* Avoid dependence on lj_jit.h if only including lj_target.h. */
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161 #define exitstub_addr(J, exitno) \
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162 ((MCode *)exitstub_addr_((char **)((J)->exitstubgroup), (exitno)))
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163 #endif
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164
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165 #endif