/home/mrjunejune/zenbu: third_party/luajit/src/lj_asm

annotate third_party/luajit/src/lj_asm_x86.h @ 279:b3b547563ec7

Add Google connector service and agent wiki Implement the C/Seobeo Google Drive and Gmail connector with encrypted OAuth storage, Zenbu authentication, browser testing, AI tool discovery, chunked HTTP decoding, and Bazel coverage. Consolidate repository guidance into progressive wiki documentation and enforce arena-first allocation for new first-party C code. Co-authored-by: Copilot <[email protected]> Copilot-Session: 84c338fd-0939-4bb3-b7f3-1062eb213e5d

author	MrJuneJune <me@mrjunejune.com>
date	Mon, 17 Aug 2026 22:22:36 -0700
parents	94705b5986b3
children

rev	line source
178 94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1 /*
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2 ** x86/x64 IR assembler (SSA IR -> machine code).
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3 ** Copyright (C) 2005-2023 Mike Pall. See Copyright Notice in luajit.h
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	4 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	5
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	6 /* -- Guard handling ------------------------------------------------------ */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	7
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	8 /* Generate an exit stub group at the bottom of the reserved MCode memory. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	9 static MCode asm_exitstub_gen(ASMState as, ExitNo group)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	10 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	11 ExitNo i, groupofs = (group*EXITSTUBS_PER_GROUP) & 0xff;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	12 MCode *mxp = as->mcbot;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	13 MCode *mxpstart = mxp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	14 if (mxp + (2+2)*EXITSTUBS_PER_GROUP+8+5 >= as->mctop)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	15 asm_mclimit(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	16 /* Push low byte of exitno for each exit stub. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	17 mxp++ = XI_PUSHi8; mxp++ = (MCode)groupofs;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	18 for (i = 1; i < EXITSTUBS_PER_GROUP; i++) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	19 mxp++ = XI_JMPs; mxp++ = (MCode)((2+2)*(EXITSTUBS_PER_GROUP - i) - 2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	20 mxp++ = XI_PUSHi8; mxp++ = (MCode)(groupofs + i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	21 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	22 /* Push the high byte of the exitno for each exit stub group. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	23 mxp++ = XI_PUSHi8; mxp++ = (MCode)((group*EXITSTUBS_PER_GROUP)>>8);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	24 #if !LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	25 /* Store DISPATCH at original stack slot 0. Account for the two push ops. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	26 *mxp++ = XI_MOVmi;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	27 *mxp++ = MODRM(XM_OFS8, 0, RID_ESP);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	28 *mxp++ = MODRM(XM_SCALE1, RID_ESP, RID_ESP);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	29 mxp++ = 2sizeof(void *);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	30 (int32_t )mxp = ptr2addr(J2GG(as->J)->dispatch); mxp += 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	31 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	32 /* Jump to exit handler which fills in the ExitState. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	33 *mxp++ = XI_JMP; mxp += 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	34 ((int32_t )(mxp-4)) = jmprel(as->J, mxp, (MCode )(void )lj_vm_exit_handler);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	35 /* Commit the code for this group (even if assembly fails later on). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	36 lj_mcode_commitbot(as->J, mxp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	37 as->mcbot = mxp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	38 as->mclim = as->mcbot + MCLIM_REDZONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	39 return mxpstart;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	40 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	41
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	42 /* Setup all needed exit stubs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	43 static void asm_exitstub_setup(ASMState *as, ExitNo nexits)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	44 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	45 ExitNo i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	46 if (nexits >= EXITSTUBS_PER_GROUP*LJ_MAX_EXITSTUBGR)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	47 lj_trace_err(as->J, LJ_TRERR_SNAPOV);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	48 for (i = 0; i < (nexits+EXITSTUBS_PER_GROUP-1)/EXITSTUBS_PER_GROUP; i++)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	49 if (as->J->exitstubgroup[i] == NULL)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	50 as->J->exitstubgroup[i] = asm_exitstub_gen(as, i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	51 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	52
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	53 /* Emit conditional branch to exit for guard.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	54 ** It's important to emit this after all registers have been allocated,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	55 ** because rematerializations may invalidate the flags.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	56 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	57 static void asm_guardcc(ASMState *as, int cc)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	58 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	59 MCode *target = exitstub_addr(as->J, as->snapno);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	60 MCode *p = as->mcp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	61 if (LJ_UNLIKELY(p == as->invmcp)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	62 as->loopinv = 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	63 (int32_t )(p+1) = jmprel(as->J, p+5, target);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	64 target = p;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	65 cc ^= 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	66 if (as->realign) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	67 if (LJ_GC64 && LJ_UNLIKELY(as->mrm.base == RID_RIP))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	68 as->mrm.ofs += 2; /* Fixup RIP offset for pending fused load. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	69 emit_sjcc(as, cc, target);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	70 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	71 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	72 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	73 if (LJ_GC64 && LJ_UNLIKELY(as->mrm.base == RID_RIP))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	74 as->mrm.ofs += 6; /* Fixup RIP offset for pending fused load. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	75 emit_jcc(as, cc, target);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	76 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	77
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	78 /* -- Memory operand fusion ----------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	79
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	80 /* Limit linear search to this distance. Avoids O(n^2) behavior. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	81 #define CONFLICT_SEARCH_LIM 31
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	82
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	83 /* Check if a reference is a signed 32 bit constant. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	84 static int asm_isk32(ASMState as, IRRef ref, int32_t k)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	85 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	86 if (irref_isk(ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	87 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	88 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	89 if (ir->o == IR_KNULL \|\| !irt_is64(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	90 *k = ir->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	91 return 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	92 } else if (checki32((int64_t)ir_k64(ir)->u64)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	93 *k = (int32_t)ir_k64(ir)->u64;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	94 return 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	95 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	96 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	97 if (ir->o != IR_KINT64) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	98 *k = ir->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	99 return 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	100 } else if (checki32((int64_t)ir_kint64(ir)->u64)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	101 *k = (int32_t)ir_kint64(ir)->u64;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	102 return 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	103 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	104 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	105 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	106 return 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	107 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	108
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	109 /* Check if there's no conflicting instruction between curins and ref.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	110 ** Also avoid fusing loads if there are multiple references.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	111 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	112 static int noconflict(ASMState *as, IRRef ref, IROp conflict, int noload)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	113 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	114 IRIns *ir = as->ir;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	115 IRRef i = as->curins;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	116 if (i > ref + CONFLICT_SEARCH_LIM)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	117 return 0; /* Give up, ref is too far away. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	118 while (--i > ref) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	119 if (ir[i].o == conflict)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	120 return 0; /* Conflict found. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	121 else if (!noload && (ir[i].op1 == ref \|\| ir[i].op2 == ref))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	122 return 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	123 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	124 return 1; /* Ok, no conflict. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	125 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	126
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	127 /* Fuse array base into memory operand. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	128 static IRRef asm_fuseabase(ASMState *as, IRRef ref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	129 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	130 IRIns *irb = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	131 as->mrm.ofs = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	132 if (irb->o == IR_FLOAD) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	133 IRIns *ira = IR(irb->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	134 lj_assertA(irb->op2 == IRFL_TAB_ARRAY, "expected FLOAD TAB_ARRAY");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	135 /* We can avoid the FLOAD of t->array for colocated arrays. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	136 if (ira->o == IR_TNEW && ira->op1 <= LJ_MAX_COLOSIZE &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	137 !neverfuse(as) && noconflict(as, irb->op1, IR_NEWREF, 1)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	138 as->mrm.ofs = (int32_t)sizeof(GCtab); /* Ofs to colocated array. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	139 return irb->op1; /* Table obj. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	140 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	141 } else if (irb->o == IR_ADD && irref_isk(irb->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	142 /* Fuse base offset (vararg load). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	143 as->mrm.ofs = IR(irb->op2)->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	144 return irb->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	145 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	146 return ref; /* Otherwise use the given array base. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	147 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	148
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	149 /* Fuse array reference into memory operand. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	150 static void asm_fusearef(ASMState as, IRIns ir, RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	151 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	152 IRIns *irx;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	153 lj_assertA(ir->o == IR_AREF, "expected AREF");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	154 as->mrm.base = (uint8_t)ra_alloc1(as, asm_fuseabase(as, ir->op1), allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	155 irx = IR(ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	156 if (irref_isk(ir->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	157 as->mrm.ofs += 8*irx->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	158 as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	159 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	160 rset_clear(allow, as->mrm.base);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	161 as->mrm.scale = XM_SCALE8;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	162 /* Fuse a constant ADD (e.g. t[i+1]) into the offset.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	163 ** Doesn't help much without ABCelim, but reduces register pressure.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	164 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	165 if (!LJ_64 && /* Has bad effects with negative index on x64. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	166 mayfuse(as, ir->op2) && ra_noreg(irx->r) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	167 irx->o == IR_ADD && irref_isk(irx->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	168 as->mrm.ofs += 8*IR(irx->op2)->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	169 as->mrm.idx = (uint8_t)ra_alloc1(as, irx->op1, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	170 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	171 as->mrm.idx = (uint8_t)ra_alloc1(as, ir->op2, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	172 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	173 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	174 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	175
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	176 /* Fuse array/hash/upvalue reference into memory operand.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	177 ** Caveat: this may allocate GPRs for the base/idx registers. Be sure to
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	178 ** pass the final allow mask, excluding any GPRs used for other inputs.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	179 ** In particular: 2-operand GPR instructions need to call ra_dest() first!
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	180 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	181 static void asm_fuseahuref(ASMState *as, IRRef ref, RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	182 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	183 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	184 if (ra_noreg(ir->r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	185 switch ((IROp)ir->o) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	186 case IR_AREF:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	187 if (mayfuse(as, ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	188 asm_fusearef(as, ir, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	189 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	190 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	191 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	192 case IR_HREFK:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	193 if (mayfuse(as, ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	194 as->mrm.base = (uint8_t)ra_alloc1(as, ir->op1, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	195 as->mrm.ofs = (int32_t)(IR(ir->op2)->op2 * sizeof(Node));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	196 as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	197 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	198 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	199 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	200 case IR_UREFC:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	201 if (irref_isk(ir->op1)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	202 GCfunc *fn = ir_kfunc(IR(ir->op1));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	203 GCupval *uv = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	204 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	205 int64_t ofs = dispofs(as, &uv->tv);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	206 if (checki32(ofs) && checki32(ofs+4)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	207 as->mrm.ofs = (int32_t)ofs;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	208 as->mrm.base = RID_DISPATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	209 as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	210 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	211 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	212 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	213 as->mrm.ofs = ptr2addr(&uv->tv);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	214 as->mrm.base = as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	215 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	216 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	217 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	218 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	219 case IR_TMPREF:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	220 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	221 as->mrm.ofs = (int32_t)dispofs(as, &J2G(as->J)->tmptv);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	222 as->mrm.base = RID_DISPATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	223 as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	224 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	225 as->mrm.ofs = igcptr(&J2G(as->J)->tmptv);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	226 as->mrm.base = as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	227 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	228 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	229 default:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	230 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	231 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	232 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	233 as->mrm.base = (uint8_t)ra_alloc1(as, ref, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	234 as->mrm.ofs = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	235 as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	236 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	237
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	238 /* Fuse FLOAD/FREF reference into memory operand. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	239 static void asm_fusefref(ASMState as, IRIns ir, RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	240 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	241 lj_assertA(ir->o == IR_FLOAD \|\| ir->o == IR_FREF,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	242 "bad IR op %d", ir->o);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	243 as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	244 if (ir->op1 == REF_NIL) { /* FLOAD from GG_State with offset. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	245 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	246 as->mrm.ofs = (int32_t)(ir->op2 << 2) - GG_OFS(dispatch);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	247 as->mrm.base = RID_DISPATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	248 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	249 as->mrm.ofs = (int32_t)(ir->op2 << 2) + ptr2addr(J2GG(as->J));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	250 as->mrm.base = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	251 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	252 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	253 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	254 as->mrm.ofs = field_ofs[ir->op2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	255 if (irref_isk(ir->op1)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	256 IRIns *op1 = IR(ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	257 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	258 if (ir->op1 == REF_NIL) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	259 as->mrm.ofs -= GG_OFS(dispatch);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	260 as->mrm.base = RID_DISPATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	261 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	262 } else if (op1->o == IR_KPTR \|\| op1->o == IR_KKPTR) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	263 intptr_t ofs = dispofs(as, ir_kptr(op1));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	264 if (checki32(as->mrm.ofs + ofs)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	265 as->mrm.ofs += (int32_t)ofs;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	266 as->mrm.base = RID_DISPATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	267 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	268 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	269 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	270 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	271 as->mrm.ofs += op1->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	272 as->mrm.base = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	273 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	274 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	275 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	276 as->mrm.base = (uint8_t)ra_alloc1(as, ir->op1, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	277 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	278
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	279 /* Fuse string reference into memory operand. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	280 static void asm_fusestrref(ASMState as, IRIns ir, RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	281 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	282 IRIns *irr;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	283 lj_assertA(ir->o == IR_STRREF, "bad IR op %d", ir->o);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	284 as->mrm.base = as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	285 as->mrm.scale = XM_SCALE1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	286 as->mrm.ofs = sizeof(GCstr);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	287 if (!LJ_GC64 && irref_isk(ir->op1)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	288 as->mrm.ofs += IR(ir->op1)->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	289 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	290 Reg r = ra_alloc1(as, ir->op1, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	291 rset_clear(allow, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	292 as->mrm.base = (uint8_t)r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	293 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	294 irr = IR(ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	295 if (irref_isk(ir->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	296 as->mrm.ofs += irr->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	297 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	298 Reg r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	299 /* Fuse a constant add into the offset, e.g. string.sub(s, i+10). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	300 if (!LJ_64 && /* Has bad effects with negative index on x64. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	301 mayfuse(as, ir->op2) && irr->o == IR_ADD && irref_isk(irr->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	302 as->mrm.ofs += IR(irr->op2)->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	303 r = ra_alloc1(as, irr->op1, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	304 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	305 r = ra_alloc1(as, ir->op2, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	306 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	307 if (as->mrm.base == RID_NONE)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	308 as->mrm.base = (uint8_t)r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	309 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	310 as->mrm.idx = (uint8_t)r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	311 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	312 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	313
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	314 static void asm_fusexref(ASMState *as, IRRef ref, RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	315 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	316 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	317 as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	318 if (ir->o == IR_KPTR \|\| ir->o == IR_KKPTR) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	319 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	320 intptr_t ofs = dispofs(as, ir_kptr(ir));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	321 if (checki32(ofs)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	322 as->mrm.ofs = (int32_t)ofs;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	323 as->mrm.base = RID_DISPATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	324 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	325 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	326 } if (0) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	327 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	328 as->mrm.ofs = ir->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	329 as->mrm.base = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	330 } else if (ir->o == IR_STRREF) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	331 asm_fusestrref(as, ir, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	332 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	333 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	334 as->mrm.ofs = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	335 if (canfuse(as, ir) && ir->o == IR_ADD && ra_noreg(ir->r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	336 /* Gather (base+idxsz)+ofs as emitted by cdata ptr/array indexing. /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	337 IRIns *irx;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	338 IRRef idx;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	339 Reg r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	340 if (asm_isk32(as, ir->op2, &as->mrm.ofs)) { /* Recognize x+ofs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	341 ref = ir->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	342 ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	343 if (!(ir->o == IR_ADD && canfuse(as, ir) && ra_noreg(ir->r)))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	344 goto noadd;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	345 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	346 as->mrm.scale = XM_SCALE1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	347 idx = ir->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	348 ref = ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	349 irx = IR(idx);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	350 if (!(irx->o == IR_BSHL \|\| irx->o == IR_ADD)) { /* Try other operand. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	351 idx = ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	352 ref = ir->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	353 irx = IR(idx);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	354 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	355 if (canfuse(as, irx) && ra_noreg(irx->r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	356 if (irx->o == IR_BSHL && irref_isk(irx->op2) && IR(irx->op2)->i <= 3) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	357 /* Recognize idx<<b with b = 0-3, corresponding to sz = (1),2,4,8. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	358 idx = irx->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	359 as->mrm.scale = (uint8_t)(IR(irx->op2)->i << 6);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	360 } else if (irx->o == IR_ADD && irx->op1 == irx->op2) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	361 /* FOLD does idx2 ==> idx<<1 ==> idx+idx. /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	362 idx = irx->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	363 as->mrm.scale = XM_SCALE2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	364 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	365 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	366 r = ra_alloc1(as, idx, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	367 rset_clear(allow, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	368 as->mrm.idx = (uint8_t)r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	369 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	370 noadd:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	371 as->mrm.base = (uint8_t)ra_alloc1(as, ref, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	372 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	373 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	374
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	375 /* Fuse load of 64 bit IR constant into memory operand. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	376 static Reg asm_fuseloadk64(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	377 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	378 const uint64_t *k = &ir_k64(ir)->u64;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	379 if (!LJ_GC64 \|\| checki32((intptr_t)k)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	380 as->mrm.ofs = ptr2addr(k);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	381 as->mrm.base = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	382 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	383 } else if (checki32(dispofs(as, k))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	384 as->mrm.ofs = (int32_t)dispofs(as, k);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	385 as->mrm.base = RID_DISPATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	386 } else if (checki32(mcpofs(as, k)) && checki32(mcpofs(as, k+1)) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	387 checki32(mctopofs(as, k)) && checki32(mctopofs(as, k+1))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	388 as->mrm.ofs = (int32_t)mcpofs(as, k);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	389 as->mrm.base = RID_RIP;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	390 } else { /* Intern 64 bit constant at bottom of mcode. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	391 if (ir->i) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	392 lj_assertA(k == (uint64_t*)(as->mctop - ir->i),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	393 "bad interned 64 bit constant");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	394 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	395 while ((uintptr_t)as->mcbot & 7) *as->mcbot++ = XI_INT3;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	396 (uint64_t)as->mcbot = *k;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	397 ir->i = (int32_t)(as->mctop - as->mcbot);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	398 as->mcbot += 8;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	399 as->mclim = as->mcbot + MCLIM_REDZONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	400 lj_mcode_commitbot(as->J, as->mcbot);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	401 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	402 as->mrm.ofs = (int32_t)mcpofs(as, as->mctop - ir->i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	403 as->mrm.base = RID_RIP;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	404 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	405 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	406 as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	407 return RID_MRM;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	408 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	409
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	410 /* Fuse load into memory operand.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	411 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	412 ** Important caveat: this may emit RIP-relative loads! So don't place any
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	413 ** code emitters between this function and the use of its result.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	414 ** The only permitted exception is asm_guardcc().
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	415 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	416 static Reg asm_fuseload(ASMState *as, IRRef ref, RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	417 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	418 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	419 if (ra_hasreg(ir->r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	420 if (allow != RSET_EMPTY) { /* Fast path. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	421 ra_noweak(as, ir->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	422 return ir->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	423 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	424 fusespill:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	425 /* Force a spill if only memory operands are allowed (asm_x87load). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	426 as->mrm.base = RID_ESP;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	427 as->mrm.ofs = ra_spill(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	428 as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	429 return RID_MRM;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	430 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	431 if (ir->o == IR_KNUM) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	432 RegSet avail = as->freeset & ~as->modset & RSET_FPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	433 lj_assertA(allow != RSET_EMPTY, "no register allowed");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	434 if (!(avail & (avail-1))) /* Fuse if less than two regs available. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	435 return asm_fuseloadk64(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	436 } else if (ref == REF_BASE \|\| ir->o == IR_KINT64) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	437 RegSet avail = as->freeset & ~as->modset & RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	438 lj_assertA(allow != RSET_EMPTY, "no register allowed");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	439 if (!(avail & (avail-1))) { /* Fuse if less than two regs available. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	440 if (ref == REF_BASE) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	441 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	442 as->mrm.ofs = (int32_t)dispofs(as, &J2G(as->J)->jit_base);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	443 as->mrm.base = RID_DISPATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	444 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	445 as->mrm.ofs = ptr2addr(&J2G(as->J)->jit_base);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	446 as->mrm.base = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	447 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	448 as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	449 return RID_MRM;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	450 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	451 return asm_fuseloadk64(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	452 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	453 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	454 } else if (mayfuse(as, ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	455 RegSet xallow = (allow & RSET_GPR) ? allow : RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	456 if (ir->o == IR_SLOAD) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	457 if (!(ir->op2 & (IRSLOAD_PARENT\|IRSLOAD_CONVERT)) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	458 noconflict(as, ref, IR_RETF, 0) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	459 !(LJ_GC64 && irt_isaddr(ir->t))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	460 as->mrm.base = (uint8_t)ra_alloc1(as, REF_BASE, xallow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	461 as->mrm.ofs = 8*((int32_t)ir->op1-1-LJ_FR2) +
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	462 (!LJ_FR2 && (ir->op2 & IRSLOAD_FRAME) ? 4 : 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	463 as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	464 return RID_MRM;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	465 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	466 } else if (ir->o == IR_FLOAD) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	467 /* Generic fusion is only ok for 32 bit operand (but see asm_comp). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	468 if ((irt_isint(ir->t) \|\| irt_isu32(ir->t) \|\| irt_isaddr(ir->t)) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	469 noconflict(as, ref, IR_FSTORE, 0)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	470 asm_fusefref(as, ir, xallow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	471 return RID_MRM;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	472 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	473 } else if (ir->o == IR_ALOAD \|\| ir->o == IR_HLOAD \|\| ir->o == IR_ULOAD) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	474 if (noconflict(as, ref, ir->o + IRDELTA_L2S, 0) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	475 !(LJ_GC64 && irt_isaddr(ir->t))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	476 asm_fuseahuref(as, ir->op1, xallow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	477 return RID_MRM;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	478 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	479 } else if (ir->o == IR_XLOAD) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	480 /* Generic fusion is not ok for 8/16 bit operands (but see asm_comp).
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	481 ** Fusing unaligned memory operands is ok on x86 (except for SIMD types).
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	482 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	483 if ((!irt_typerange(ir->t, IRT_I8, IRT_U16)) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	484 noconflict(as, ref, IR_XSTORE, 0)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	485 asm_fusexref(as, ir->op1, xallow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	486 return RID_MRM;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	487 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	488 } else if (ir->o == IR_VLOAD && IR(ir->op1)->o == IR_AREF &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	489 !(LJ_GC64 && irt_isaddr(ir->t))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	490 asm_fuseahuref(as, ir->op1, xallow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	491 as->mrm.ofs += 8 * ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	492 return RID_MRM;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	493 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	494 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	495 if (ir->o == IR_FLOAD && ir->op1 == REF_NIL) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	496 asm_fusefref(as, ir, RSET_EMPTY);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	497 return RID_MRM;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	498 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	499 if (!(as->freeset & allow) && !emit_canremat(ref) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	500 (allow == RSET_EMPTY \|\| ra_hasspill(ir->s) \|\| iscrossref(as, ref)))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	501 goto fusespill;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	502 return ra_allocref(as, ref, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	503 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	504
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	505 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	506 /* Don't fuse a 32 bit load into a 64 bit operation. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	507 static Reg asm_fuseloadm(ASMState *as, IRRef ref, RegSet allow, int is64)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	508 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	509 if (is64 && !irt_is64(IR(ref)->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	510 return ra_alloc1(as, ref, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	511 return asm_fuseload(as, ref, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	512 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	513 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	514 #define asm_fuseloadm(as, ref, allow, is64) asm_fuseload(as, (ref), (allow))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	515 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	516
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	517 /* -- Calls --------------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	518
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	519 /* Count the required number of stack slots for a call. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	520 static int asm_count_call_slots(ASMState as, const CCallInfo ci, IRRef *args)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	521 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	522 uint32_t i, nargs = CCI_XNARGS(ci);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	523 int nslots = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	524 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	525 if (LJ_ABI_WIN) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	526 nslots = (int)(nargs2); / Only matters for more than four args. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	527 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	528 int ngpr = REGARG_NUMGPR, nfpr = REGARG_NUMFPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	529 for (i = 0; i < nargs; i++)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	530 if (args[i] && irt_isfp(IR(args[i])->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	531 if (nfpr > 0) nfpr--; else nslots += 2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	532 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	533 if (ngpr > 0) ngpr--; else nslots += 2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	534 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	535 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	536 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	537 int ngpr = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	538 if ((ci->flags & CCI_CC_MASK) == CCI_CC_FASTCALL)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	539 ngpr = 2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	540 else if ((ci->flags & CCI_CC_MASK) == CCI_CC_THISCALL)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	541 ngpr = 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	542 for (i = 0; i < nargs; i++)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	543 if (args[i] && irt_isfp(IR(args[i])->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	544 nslots += irt_isnum(IR(args[i])->t) ? 2 : 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	545 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	546 if (ngpr > 0) ngpr--; else nslots++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	547 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	548 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	549 return nslots;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	550 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	551
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	552 /* Generate a call to a C function. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	553 static void asm_gencall(ASMState as, const CCallInfo ci, IRRef *args)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	554 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	555 uint32_t n, nargs = CCI_XNARGS(ci);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	556 int32_t ofs = STACKARG_OFS;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	557 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	558 uint32_t gprs = REGARG_GPRS;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	559 Reg fpr = REGARG_FIRSTFPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	560 #if !LJ_ABI_WIN
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	561 MCode *patchnfpr = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	562 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	563 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	564 uint32_t gprs = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	565 if ((ci->flags & CCI_CC_MASK) != CCI_CC_CDECL) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	566 if ((ci->flags & CCI_CC_MASK) == CCI_CC_THISCALL)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	567 gprs = (REGARG_GPRS & 31);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	568 else if ((ci->flags & CCI_CC_MASK) == CCI_CC_FASTCALL)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	569 gprs = REGARG_GPRS;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	570 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	571 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	572 if ((void *)ci->func)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	573 emit_call(as, ci->func);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	574 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	575 if ((ci->flags & CCI_VARARG)) { /* Special handling for vararg calls. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	576 #if LJ_ABI_WIN
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	577 for (n = 0; n < 4 && n < nargs; n++) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	578 IRIns *ir = IR(args[n]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	579 if (irt_isfp(ir->t)) /* Duplicate FPRs in GPRs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	580 emit_rr(as, XO_MOVDto, (irt_isnum(ir->t) ? REX_64 : 0) \| (fpr+n),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	581 ((gprs >> (n5)) & 31)); / Either MOVD or MOVQ. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	582 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	583 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	584 patchnfpr = --as->mcp; /* Indicate number of used FPRs in register al. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	585 *--as->mcp = XI_MOVrib \| RID_EAX;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	586 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	587 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	588 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	589 for (n = 0; n < nargs; n++) { /* Setup args. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	590 IRRef ref = args[n];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	591 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	592 Reg r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	593 #if LJ_64 && LJ_ABI_WIN
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	594 /* Windows/x64 argument registers are strictly positional. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	595 r = irt_isfp(ir->t) ? (fpr <= REGARG_LASTFPR ? fpr : 0) : (gprs & 31);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	596 fpr++; gprs >>= 5;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	597 #elif LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	598 /* POSIX/x64 argument registers are used in order of appearance. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	599 if (irt_isfp(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	600 r = fpr <= REGARG_LASTFPR ? fpr++ : 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	601 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	602 r = gprs & 31; gprs >>= 5;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	603 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	604 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	605 if (ref && irt_isfp(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	606 r = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	607 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	608 r = gprs & 31; gprs >>= 5;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	609 if (!ref) continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	610 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	611 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	612 if (r) { /* Argument is in a register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	613 if (r < RID_MAX_GPR && ref < ASMREF_TMP1) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	614 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	615 if (LJ_GC64 ? !(ir->o == IR_KINT \|\| ir->o == IR_KNULL) : ir->o == IR_KINT64)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	616 emit_loadu64(as, r, ir_k64(ir)->u64);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	617 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	618 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	619 emit_loadi(as, r, ir->i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	620 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	621 /* Must have been evicted. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	622 lj_assertA(rset_test(as->freeset, r), "reg %d not free", r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	623 if (ra_hasreg(ir->r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	624 ra_noweak(as, ir->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	625 emit_movrr(as, ir, r, ir->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	626 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	627 ra_allocref(as, ref, RID2RSET(r));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	628 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	629 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	630 } else if (irt_isfp(ir->t)) { /* FP argument is on stack. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	631 lj_assertA(!(irt_isfloat(ir->t) && irref_isk(ref)),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	632 "unexpected float constant");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	633 if (LJ_32 && (ofs & 4) && irref_isk(ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	634 /* Split stores for unaligned FP consts. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	635 emit_movmroi(as, RID_ESP, ofs, (int32_t)ir_knum(ir)->u32.lo);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	636 emit_movmroi(as, RID_ESP, ofs+4, (int32_t)ir_knum(ir)->u32.hi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	637 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	638 r = ra_alloc1(as, ref, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	639 emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSDto : XO_MOVSSto,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	640 r, RID_ESP, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	641 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	642 ofs += (LJ_32 && irt_isfloat(ir->t)) ? 4 : 8;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	643 } else { /* Non-FP argument is on stack. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	644 if (LJ_32 && ref < ASMREF_TMP1) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	645 emit_movmroi(as, RID_ESP, ofs, ir->i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	646 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	647 r = ra_alloc1(as, ref, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	648 emit_movtomro(as, REX_64 + r, RID_ESP, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	649 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	650 ofs += sizeof(intptr_t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	651 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	652 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	653 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	654 #if LJ_64 && !LJ_ABI_WIN
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	655 if (patchnfpr) *patchnfpr = fpr - REGARG_FIRSTFPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	656 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	657 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	658
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	659 /* Setup result reg/sp for call. Evict scratch regs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	660 static void asm_setupresult(ASMState as, IRIns ir, const CCallInfo *ci)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	661 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	662 RegSet drop = RSET_SCRATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	663 int hiop = ((ir+1)->o == IR_HIOP && !irt_isnil((ir+1)->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	664 if ((ci->flags & CCI_NOFPRCLOBBER))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	665 drop &= ~RSET_FPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	666 if (ra_hasreg(ir->r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	667 rset_clear(drop, ir->r); /* Dest reg handled below. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	668 if (hiop && ra_hasreg((ir+1)->r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	669 rset_clear(drop, (ir+1)->r); /* Dest reg handled below. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	670 ra_evictset(as, drop); /* Evictions must be performed first. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	671 if (ra_used(ir)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	672 if (irt_isfp(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	673 int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	674 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	675 if ((ci->flags & CCI_CASTU64)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	676 Reg dest = ir->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	677 if (ra_hasreg(dest)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	678 ra_free(as, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	679 ra_modified(as, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	680 emit_rr(as, XO_MOVD, dest\|REX_64, RID_RET); /* Really MOVQ. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	681 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	682 if (ofs) emit_movtomro(as, RID_RET\|REX_64, RID_ESP, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	683 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	684 ra_destreg(as, ir, RID_FPRET);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	685 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	686 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	687 /* Number result is in x87 st0 for x86 calling convention. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	688 Reg dest = ir->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	689 if (ra_hasreg(dest)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	690 ra_free(as, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	691 ra_modified(as, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	692 emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSD : XO_MOVSS,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	693 dest, RID_ESP, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	694 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	695 if ((ci->flags & CCI_CASTU64)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	696 emit_movtomro(as, RID_RETLO, RID_ESP, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	697 emit_movtomro(as, RID_RETHI, RID_ESP, ofs+4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	698 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	699 emit_rmro(as, irt_isnum(ir->t) ? XO_FSTPq : XO_FSTPd,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	700 irt_isnum(ir->t) ? XOg_FSTPq : XOg_FSTPd, RID_ESP, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	701 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	702 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	703 } else if (hiop) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	704 ra_destpair(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	705 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	706 lj_assertA(!irt_ispri(ir->t), "PRI dest");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	707 ra_destreg(as, ir, RID_RET);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	708 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	709 } else if (LJ_32 && irt_isfp(ir->t) && !(ci->flags & CCI_CASTU64)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	710 emit_x87op(as, XI_FPOP); /* Pop unused result from x87 st0. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	711 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	712 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	713
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	714 /* Return a constant function pointer or NULL for indirect calls. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	715 static void asm_callx_func(ASMState as, IRIns *irf, IRRef func)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	716 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	717 #if LJ_32
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	718 UNUSED(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	719 if (irref_isk(func))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	720 return (void *)irf->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	721 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	722 if (irref_isk(func)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	723 MCode *p;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	724 if (irf->o == IR_KINT64)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	725 p = (MCode )(void )ir_k64(irf)->u64;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	726 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	727 p = (MCode )(void )(uintptr_t)(uint32_t)irf->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	728 if (p - as->mcp == (int32_t)(p - as->mcp))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	729 return p; /* Call target is still in +-2GB range. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	730 /* Avoid the indirect case of emit_call(). Try to hoist func addr. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	731 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	732 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	733 return NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	734 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	735
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	736 static void asm_callx(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	737 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	738 IRRef args[CCI_NARGS_MAX*2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	739 CCallInfo ci;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	740 IRRef func;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	741 IRIns *irf;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	742 int32_t spadj = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	743 ci.flags = asm_callx_flags(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	744 asm_collectargs(as, ir, &ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	745 asm_setupresult(as, ir, &ci);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	746 #if LJ_32
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	747 /* Have to readjust stack after non-cdecl calls due to callee cleanup. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	748 if ((ci.flags & CCI_CC_MASK) != CCI_CC_CDECL)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	749 spadj = 4 * asm_count_call_slots(as, &ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	750 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	751 func = ir->op2; irf = IR(func);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	752 if (irf->o == IR_CARG) { func = irf->op1; irf = IR(func); }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	753 ci.func = (ASMFunction)asm_callx_func(as, irf, func);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	754 if (!(void *)ci.func) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	755 /* Use a (hoistable) non-scratch register for indirect calls. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	756 RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	757 Reg r = ra_alloc1(as, func, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	758 if (LJ_32) emit_spsub(as, spadj); /* Above code may cause restores! */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	759 emit_rr(as, XO_GROUP5, XOg_CALL, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	760 } else if (LJ_32) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	761 emit_spsub(as, spadj);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	762 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	763 asm_gencall(as, &ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	764 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	765
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	766 /* -- Returns ------------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	767
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	768 /* Return to lower frame. Guard that it goes to the right spot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	769 static void asm_retf(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	770 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	771 Reg base = ra_alloc1(as, REF_BASE, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	772 #if LJ_FR2
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	773 Reg rpc = ra_scratch(as, rset_exclude(RSET_GPR, base));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	774 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	775 void *pc = ir_kptr(IR(ir->op2));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	776 int32_t delta = 1+LJ_FR2+bc_a(((const BCIns )pc - 1));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	777 as->topslot -= (BCReg)delta;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	778 if ((int32_t)as->topslot < 0) as->topslot = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	779 irt_setmark(IR(REF_BASE)->t); /* Children must not coalesce with BASE reg. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	780 emit_setgl(as, base, jit_base);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	781 emit_addptr(as, base, -8*delta);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	782 asm_guardcc(as, CC_NE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	783 #if LJ_FR2
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	784 emit_rmro(as, XO_CMP, rpc\|REX_GC64, base, -8);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	785 emit_loadu64(as, rpc, u64ptr(pc));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	786 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	787 emit_gmroi(as, XG_ARITHi(XOg_CMP), base, -4, ptr2addr(pc));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	788 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	789 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	790
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	791 /* -- Buffer operations --------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	792
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	793 #if LJ_HASBUFFER
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	794 static void asm_bufhdr_write(ASMState *as, Reg sb)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	795 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	796 Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, sb));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	797 IRIns irgc;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	798 irgc.ot = IRT(0, IRT_PGC); /* GC type. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	799 emit_storeofs(as, &irgc, tmp, sb, offsetof(SBuf, L));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	800 emit_opgl(as, XO_ARITH(XOg_OR), tmp\|REX_GC64, cur_L);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	801 emit_gri(as, XG_ARITHi(XOg_AND), tmp, SBUF_MASK_FLAG);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	802 emit_loadofs(as, &irgc, tmp, sb, offsetof(SBuf, L));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	803 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	804 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	805
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	806 /* -- Type conversions ---------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	807
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	808 static void asm_tointg(ASMState as, IRIns ir, Reg left)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	809 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	810 Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	811 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	812 asm_guardcc(as, CC_P);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	813 asm_guardcc(as, CC_NE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	814 emit_rr(as, XO_UCOMISD, left, tmp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	815 emit_rr(as, XO_CVTSI2SD, tmp, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	816 emit_rr(as, XO_XORPS, tmp, tmp); /* Avoid partial register stall. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	817 emit_rr(as, XO_CVTTSD2SI, dest, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	818 /* Can't fuse since left is needed twice. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	819 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	820
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	821 static void asm_tobit(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	822 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	823 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	824 Reg tmp = ra_noreg(IR(ir->op1)->r) ?
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	825 ra_alloc1(as, ir->op1, RSET_FPR) :
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	826 ra_scratch(as, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	827 Reg right;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	828 emit_rr(as, XO_MOVDto, tmp, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	829 right = asm_fuseload(as, ir->op2, rset_exclude(RSET_FPR, tmp));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	830 emit_mrm(as, XO_ADDSD, tmp, right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	831 ra_left(as, tmp, ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	832 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	833
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	834 static void asm_conv(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	835 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	836 IRType st = (IRType)(ir->op2 & IRCONV_SRCMASK);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	837 int st64 = (st == IRT_I64 \|\| st == IRT_U64 \|\| (LJ_64 && st == IRT_P64));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	838 int stfp = (st == IRT_NUM \|\| st == IRT_FLOAT);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	839 IRRef lref = ir->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	840 lj_assertA(irt_type(ir->t) != st, "inconsistent types for CONV");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	841 lj_assertA(!(LJ_32 && (irt_isint64(ir->t) \|\| st64)),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	842 "IR %04d has unsplit 64 bit type",
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	843 (int)(ir - as->ir) - REF_BIAS);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	844 if (irt_isfp(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	845 Reg dest = ra_dest(as, ir, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	846 if (stfp) { /* FP to FP conversion. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	847 Reg left = asm_fuseload(as, lref, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	848 emit_mrm(as, st == IRT_NUM ? XO_CVTSD2SS : XO_CVTSS2SD, dest, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	849 if (left == dest) return; /* Avoid the XO_XORPS. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	850 } else if (LJ_32 && st == IRT_U32) { /* U32 to FP conversion on x86. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	851 /* number = (2^52+2^51 .. u32) - (2^52+2^51) */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	852 cTValue *k = &as->J->k64[LJ_K64_TOBIT];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	853 Reg bias = ra_scratch(as, rset_exclude(RSET_FPR, dest));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	854 if (irt_isfloat(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	855 emit_rr(as, XO_CVTSD2SS, dest, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	856 emit_rr(as, XO_SUBSD, dest, bias); /* Subtract 2^52+2^51 bias. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	857 emit_rr(as, XO_XORPS, dest, bias); /* Merge bias and integer. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	858 emit_rma(as, XO_MOVSD, bias, k);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	859 emit_mrm(as, XO_MOVD, dest, asm_fuseload(as, lref, RSET_GPR));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	860 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	861 } else { /* Integer to FP conversion. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	862 Reg left = (LJ_64 && (st == IRT_U32 \|\| st == IRT_U64)) ?
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	863 ra_alloc1(as, lref, RSET_GPR) :
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	864 asm_fuseloadm(as, lref, RSET_GPR, st64);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	865 if (LJ_64 && st == IRT_U64) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	866 MCLabel l_end = emit_label(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	867 cTValue *k = &as->J->k64[LJ_K64_2P64];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	868 emit_rma(as, XO_ADDSD, dest, k); /* Add 2^64 to compensate. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	869 emit_sjcc(as, CC_NS, l_end);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	870 emit_rr(as, XO_TEST, left\|REX_64, left); /* Check if u64 >= 2^63. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	871 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	872 emit_mrm(as, irt_isnum(ir->t) ? XO_CVTSI2SD : XO_CVTSI2SS,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	873 dest\|((LJ_64 && (st64 \|\| st == IRT_U32)) ? REX_64 : 0), left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	874 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	875 emit_rr(as, XO_XORPS, dest, dest); /* Avoid partial register stall. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	876 } else if (stfp) { /* FP to integer conversion. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	877 if (irt_isguard(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	878 /* Checked conversions are only supported from number to int. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	879 lj_assertA(irt_isint(ir->t) && st == IRT_NUM,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	880 "bad type for checked CONV");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	881 asm_tointg(as, ir, ra_alloc1(as, lref, RSET_FPR));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	882 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	883 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	884 x86Op op = st == IRT_NUM ? XO_CVTTSD2SI : XO_CVTTSS2SI;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	885 if (LJ_64 ? irt_isu64(ir->t) : irt_isu32(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	886 /* LJ_64: For inputs >= 2^63 add -2^64, convert again. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	887 /* LJ_32: For inputs >= 2^31 add -2^31, convert again and add 2^31. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	888 Reg tmp = ra_noreg(IR(lref)->r) ? ra_alloc1(as, lref, RSET_FPR) :
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	889 ra_scratch(as, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	890 MCLabel l_end = emit_label(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	891 if (LJ_32)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	892 emit_gri(as, XG_ARITHi(XOg_ADD), dest, (int32_t)0x80000000);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	893 emit_rr(as, op, dest\|REX_64, tmp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	894 if (st == IRT_NUM)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	895 emit_rma(as, XO_ADDSD, tmp, &as->J->k64[LJ_K64_M2P64_31]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	896 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	897 emit_rma(as, XO_ADDSS, tmp, &as->J->k32[LJ_K32_M2P64_31]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	898 emit_sjcc(as, CC_NS, l_end);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	899 emit_rr(as, XO_TEST, dest\|REX_64, dest); /* Check if dest negative. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	900 emit_rr(as, op, dest\|REX_64, tmp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	901 ra_left(as, tmp, lref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	902 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	903 if (LJ_64 && irt_isu32(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	904 emit_rr(as, XO_MOV, dest, dest); /* Zero hiword. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	905 emit_mrm(as, op,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	906 dest\|((LJ_64 &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	907 (irt_is64(ir->t) \|\| irt_isu32(ir->t))) ? REX_64 : 0),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	908 asm_fuseload(as, lref, RSET_FPR));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	909 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	910 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	911 } else if (st >= IRT_I8 && st <= IRT_U16) { /* Extend to 32 bit integer. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	912 Reg left, dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	913 RegSet allow = RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	914 x86Op op;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	915 lj_assertA(irt_isint(ir->t) \|\| irt_isu32(ir->t), "bad type for CONV EXT");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	916 if (st == IRT_I8) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	917 op = XO_MOVSXb; allow = RSET_GPR8; dest \|= FORCE_REX;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	918 } else if (st == IRT_U8) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	919 op = XO_MOVZXb; allow = RSET_GPR8; dest \|= FORCE_REX;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	920 } else if (st == IRT_I16) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	921 op = XO_MOVSXw;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	922 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	923 op = XO_MOVZXw;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	924 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	925 left = asm_fuseload(as, lref, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	926 /* Add extra MOV if source is already in wrong register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	927 if (!LJ_64 && left != RID_MRM && !rset_test(allow, left)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	928 Reg tmp = ra_scratch(as, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	929 emit_rr(as, op, dest, tmp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	930 emit_rr(as, XO_MOV, tmp, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	931 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	932 emit_mrm(as, op, dest, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	933 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	934 } else { /* 32/64 bit integer conversions. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	935 if (LJ_32) { /* Only need to handle 32/32 bit no-op (cast) on x86. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	936 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	937 ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	938 } else if (irt_is64(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	939 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	940 if (st64 \|\| !(ir->op2 & IRCONV_SEXT)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	941 /* 64/64 bit no-op (cast) or 32 to 64 bit zero extension. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	942 ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	943 } else { /* 32 to 64 bit sign extension. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	944 Reg left = asm_fuseload(as, lref, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	945 emit_mrm(as, XO_MOVSXd, dest\|REX_64, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	946 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	947 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	948 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	949 if (st64 && !(ir->op2 & IRCONV_NONE)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	950 Reg left = asm_fuseload(as, lref, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	951 /* This is either a 32 bit reg/reg mov which zeroes the hiword
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	952 ** or a load of the loword from a 64 bit address.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	953 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	954 emit_mrm(as, XO_MOV, dest, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	955 } else { /* 32/32 bit no-op (cast). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	956 ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	957 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	958 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	959 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	960 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	961
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	962 #if LJ_32 && LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	963 /* No SSE conversions to/from 64 bit on x86, so resort to ugly x87 code. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	964
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	965 /* 64 bit integer to FP conversion in 32 bit mode. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	966 static void asm_conv_fp_int64(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	967 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	968 Reg hi = ra_alloc1(as, ir->op1, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	969 Reg lo = ra_alloc1(as, (ir-1)->op1, rset_exclude(RSET_GPR, hi));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	970 int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	971 Reg dest = ir->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	972 if (ra_hasreg(dest)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	973 ra_free(as, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	974 ra_modified(as, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	975 emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSD : XO_MOVSS, dest, RID_ESP, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	976 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	977 emit_rmro(as, irt_isnum(ir->t) ? XO_FSTPq : XO_FSTPd,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	978 irt_isnum(ir->t) ? XOg_FSTPq : XOg_FSTPd, RID_ESP, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	979 if (((ir-1)->op2 & IRCONV_SRCMASK) == IRT_U64) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	980 /* For inputs in [2^63,2^64-1] add 2^64 to compensate. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	981 MCLabel l_end = emit_label(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	982 emit_rma(as, XO_FADDq, XOg_FADDq, &as->J->k64[LJ_K64_2P64]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	983 emit_sjcc(as, CC_NS, l_end);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	984 emit_rr(as, XO_TEST, hi, hi); /* Check if u64 >= 2^63. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	985 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	986 lj_assertA(((ir-1)->op2 & IRCONV_SRCMASK) == IRT_I64, "bad type for CONV");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	987 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	988 emit_rmro(as, XO_FILDq, XOg_FILDq, RID_ESP, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	989 /* NYI: Avoid narrow-to-wide store-to-load forwarding stall. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	990 emit_rmro(as, XO_MOVto, hi, RID_ESP, 4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	991 emit_rmro(as, XO_MOVto, lo, RID_ESP, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	992 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	993
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	994 /* FP to 64 bit integer conversion in 32 bit mode. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	995 static void asm_conv_int64_fp(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	996 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	997 IRType st = (IRType)((ir-1)->op2 & IRCONV_SRCMASK);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	998 IRType dt = (((ir-1)->op2 & IRCONV_DSTMASK) >> IRCONV_DSH);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	999 Reg lo, hi;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1000 lj_assertA(st == IRT_NUM \|\| st == IRT_FLOAT, "bad type for CONV");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1001 lj_assertA(dt == IRT_I64 \|\| dt == IRT_U64, "bad type for CONV");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1002 hi = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1003 lo = ra_dest(as, ir-1, rset_exclude(RSET_GPR, hi));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1004 if (ra_used(ir-1)) emit_rmro(as, XO_MOV, lo, RID_ESP, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1005 /* NYI: Avoid wide-to-narrow store-to-load forwarding stall. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1006 if (!(as->flags & JIT_F_SSE3)) { /* Set FPU rounding mode to default. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1007 emit_rmro(as, XO_FLDCW, XOg_FLDCW, RID_ESP, 4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1008 emit_rmro(as, XO_MOVto, lo, RID_ESP, 4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1009 emit_gri(as, XG_ARITHi(XOg_AND), lo, 0xf3ff);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1010 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1011 if (dt == IRT_U64) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1012 /* For inputs in [2^63,2^64-1] add -2^64 and convert again. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1013 MCLabel l_pop, l_end = emit_label(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1014 emit_x87op(as, XI_FPOP);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1015 l_pop = emit_label(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1016 emit_sjmp(as, l_end);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1017 emit_rmro(as, XO_MOV, hi, RID_ESP, 4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1018 if ((as->flags & JIT_F_SSE3))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1019 emit_rmro(as, XO_FISTTPq, XOg_FISTTPq, RID_ESP, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1020 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1021 emit_rmro(as, XO_FISTPq, XOg_FISTPq, RID_ESP, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1022 emit_rma(as, XO_FADDq, XOg_FADDq, &as->J->k64[LJ_K64_M2P64]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1023 emit_sjcc(as, CC_NS, l_pop);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1024 emit_rr(as, XO_TEST, hi, hi); /* Check if out-of-range (2^63). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1025 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1026 emit_rmro(as, XO_MOV, hi, RID_ESP, 4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1027 if ((as->flags & JIT_F_SSE3)) { /* Truncation is easy with SSE3. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1028 emit_rmro(as, XO_FISTTPq, XOg_FISTTPq, RID_ESP, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1029 } else { /* Otherwise set FPU rounding mode to truncate before the store. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1030 emit_rmro(as, XO_FISTPq, XOg_FISTPq, RID_ESP, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1031 emit_rmro(as, XO_FLDCW, XOg_FLDCW, RID_ESP, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1032 emit_rmro(as, XO_MOVtow, lo, RID_ESP, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1033 emit_rmro(as, XO_ARITHw(XOg_OR), lo, RID_ESP, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1034 emit_loadi(as, lo, 0xc00);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1035 emit_rmro(as, XO_FNSTCW, XOg_FNSTCW, RID_ESP, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1036 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1037 if (dt == IRT_U64)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1038 emit_x87op(as, XI_FDUP);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1039 emit_mrm(as, st == IRT_NUM ? XO_FLDq : XO_FLDd,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1040 st == IRT_NUM ? XOg_FLDq: XOg_FLDd,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1041 asm_fuseload(as, ir->op1, RSET_EMPTY));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1042 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1043
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1044 static void asm_conv64(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1045 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1046 if (irt_isfp(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1047 asm_conv_fp_int64(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1048 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1049 asm_conv_int64_fp(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1050 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1051 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1052
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1053 static void asm_strto(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1054 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1055 /* Force a spill slot for the destination register (if any). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1056 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_strscan_num];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1057 IRRef args[2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1058 RegSet drop = RSET_SCRATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1059 if ((drop & RSET_FPR) != RSET_FPR && ra_hasreg(ir->r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1060 rset_set(drop, ir->r); /* WIN64 doesn't spill all FPRs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1061 ra_evictset(as, drop);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1062 asm_guardcc(as, CC_E);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1063 emit_rr(as, XO_TEST, RID_RET, RID_RET); /* Test return status. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1064 args[0] = ir->op1; /* GCstr str /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1065 args[1] = ASMREF_TMP1; /* TValue n /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1066 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1067 /* Store the result to the spill slot or temp slots. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1068 emit_rmro(as, XO_LEA, ra_releasetmp(as, ASMREF_TMP1)\|REX_64,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1069 RID_ESP, sps_scale(ir->s));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1070 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1071
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1072 /* -- Memory references --------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1073
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1074 /* Get pointer to TValue. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1075 static void asm_tvptr(ASMState *as, Reg dest, IRRef ref, MSize mode)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1076 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1077 if ((mode & IRTMPREF_IN1)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1078 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1079 if (irt_isnum(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1080 if (irref_isk(ref) && !(mode & IRTMPREF_OUT1)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1081 /* Use the number constant itself as a TValue. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1082 emit_loada(as, dest, ir_knum(ir));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1083 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1084 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1085 emit_rmro(as, XO_MOVSDto, ra_alloc1(as, ref, RSET_FPR), dest, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1086 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1087 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1088 if (irref_isk(ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1089 TValue k;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1090 lj_ir_kvalue(as->J->L, &k, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1091 emit_movmroi(as, dest, 4, k.u32.hi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1092 emit_movmroi(as, dest, 0, k.u32.lo);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1093 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1094 /* TODO: 64 bit store + 32 bit load-modify-store is suboptimal. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1095 Reg src = ra_alloc1(as, ref, rset_exclude(RSET_GPR, dest));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1096 if (irt_is64(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1097 emit_u32(as, irt_toitype(ir->t) << 15);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1098 emit_rmro(as, XO_ARITHi, XOg_OR, dest, 4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1099 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1100 emit_movmroi(as, dest, 4, (irt_toitype(ir->t) << 15));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1101 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1102 emit_movtomro(as, REX_64IR(ir, src), dest, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1103 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1104 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1105 if (!irref_isk(ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1106 Reg src = ra_alloc1(as, ref, rset_exclude(RSET_GPR, dest));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1107 emit_movtomro(as, REX_64IR(ir, src), dest, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1108 } else if (!irt_ispri(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1109 emit_movmroi(as, dest, 0, ir->i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1110 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1111 if (!(LJ_64 && irt_islightud(ir->t)))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1112 emit_movmroi(as, dest, 4, irt_toitype(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1113 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1114 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1115 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1116 emit_loada(as, dest, &J2G(as->J)->tmptv); /* g->tmptv holds the TValue(s). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1117 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1118
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1119 static void asm_aref(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1120 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1121 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1122 asm_fusearef(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1123 if (!(as->mrm.idx == RID_NONE && as->mrm.ofs == 0))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1124 emit_mrm(as, XO_LEA, dest\|REX_GC64, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1125 else if (as->mrm.base != dest)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1126 emit_rr(as, XO_MOV, dest\|REX_GC64, as->mrm.base);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1127 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1128
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1129 /* Inlined hash lookup. Specialized for key type and for const keys.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1130 ** The equivalent C code is:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1131 ** Node *n = hashkey(t, key);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1132 ** do {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1133 ** if (lj_obj_equal(&n->key, key)) return &n->val;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1134 ** } while ((n = nextnode(n)));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1135 ** return niltv(L);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1136 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1137 static void asm_href(ASMState as, IRIns ir, IROp merge)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1138 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1139 RegSet allow = RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1140 int destused = ra_used(ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1141 Reg dest = ra_dest(as, ir, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1142 Reg tab = ra_alloc1(as, ir->op1, rset_clear(allow, dest));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1143 Reg key = RID_NONE, tmp = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1144 IRIns *irkey = IR(ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1145 int isk = irref_isk(ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1146 IRType1 kt = irkey->t;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1147 uint32_t khash;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1148 MCLabel l_end, l_loop, l_next;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1149
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1150 if (!isk) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1151 rset_clear(allow, tab);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1152 key = ra_alloc1(as, ir->op2, irt_isnum(kt) ? RSET_FPR : allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1153 if (LJ_GC64 \|\| !irt_isstr(kt))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1154 tmp = ra_scratch(as, rset_exclude(allow, key));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1155 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1156
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1157 /* Key not found in chain: jump to exit (if merged) or load niltv. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1158 l_end = emit_label(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1159 if (merge == IR_NE)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1160 asm_guardcc(as, CC_E); /* XI_JMP is not found by lj_asm_patchexit. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1161 else if (destused)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1162 emit_loada(as, dest, niltvg(J2G(as->J)));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1163
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1164 /* Follow hash chain until the end. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1165 l_loop = emit_sjcc_label(as, CC_NZ);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1166 emit_rr(as, XO_TEST, dest\|REX_GC64, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1167 emit_rmro(as, XO_MOV, dest\|REX_GC64, dest, offsetof(Node, next));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1168 l_next = emit_label(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1169
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1170 /* Type and value comparison. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1171 if (merge == IR_EQ)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1172 asm_guardcc(as, CC_E);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1173 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1174 emit_sjcc(as, CC_E, l_end);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1175 if (irt_isnum(kt)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1176 if (isk) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1177 /* Assumes -0.0 is already canonicalized to +0.0. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1178 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.u32.lo),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1179 (int32_t)ir_knum(irkey)->u32.lo);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1180 emit_sjcc(as, CC_NE, l_next);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1181 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.u32.hi),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1182 (int32_t)ir_knum(irkey)->u32.hi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1183 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1184 emit_sjcc(as, CC_P, l_next);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1185 emit_rmro(as, XO_UCOMISD, key, dest, offsetof(Node, key.n));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1186 emit_sjcc(as, CC_AE, l_next);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1187 /* The type check avoids NaN penalties and complaints from Valgrind. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1188 #if LJ_64 && !LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1189 emit_u32(as, LJ_TISNUM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1190 emit_rmro(as, XO_ARITHi, XOg_CMP, dest, offsetof(Node, key.it));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1191 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1192 emit_i8(as, LJ_TISNUM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1193 emit_rmro(as, XO_ARITHi8, XOg_CMP, dest, offsetof(Node, key.it));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1194 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1195 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1196 #if LJ_64 && !LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1197 } else if (irt_islightud(kt)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1198 emit_rmro(as, XO_CMP, key\|REX_64, dest, offsetof(Node, key.u64));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1199 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1200 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1201 } else if (irt_isaddr(kt)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1202 if (isk) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1203 TValue k;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1204 k.u64 = ((uint64_t)irt_toitype(irkey->t) << 47) \| irkey[1].tv.u64;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1205 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.u32.lo),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1206 k.u32.lo);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1207 emit_sjcc(as, CC_NE, l_next);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1208 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.u32.hi),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1209 k.u32.hi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1210 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1211 emit_rmro(as, XO_CMP, tmp\|REX_64, dest, offsetof(Node, key.u64));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1212 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1213 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1214 lj_assertA(irt_ispri(kt) && !irt_isnil(kt), "bad HREF key type");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1215 emit_u32(as, (irt_toitype(kt)<<15)\|0x7fff);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1216 emit_rmro(as, XO_ARITHi, XOg_CMP, dest, offsetof(Node, key.it));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1217 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1218 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1219 if (!irt_ispri(kt)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1220 lj_assertA(irt_isaddr(kt), "bad HREF key type");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1221 if (isk)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1222 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.gcr),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1223 ptr2addr(ir_kgc(irkey)));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1224 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1225 emit_rmro(as, XO_CMP, key, dest, offsetof(Node, key.gcr));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1226 emit_sjcc(as, CC_NE, l_next);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1227 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1228 lj_assertA(!irt_isnil(kt), "bad HREF key type");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1229 emit_i8(as, irt_toitype(kt));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1230 emit_rmro(as, XO_ARITHi8, XOg_CMP, dest, offsetof(Node, key.it));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1231 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1232 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1233 emit_sfixup(as, l_loop);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1234 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1235 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1236 if (!isk && irt_isaddr(kt)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1237 emit_rr(as, XO_OR, tmp\|REX_64, key);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1238 emit_loadu64(as, tmp, (uint64_t)irt_toitype(kt) << 47);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1239 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1240 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1241
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1242 /* Load main position relative to tab->node into dest. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1243 khash = isk ? ir_khash(as, irkey) : 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1244 if (khash == 0) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1245 emit_rmro(as, XO_MOV, dest\|REX_GC64, tab, offsetof(GCtab, node));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1246 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1247 emit_rmro(as, XO_ARITH(XOg_ADD), dest\|REX_GC64, tab, offsetof(GCtab,node));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1248 emit_shifti(as, XOg_SHL, dest, 3);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1249 emit_rmrxo(as, XO_LEA, dest, dest, dest, XM_SCALE2, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1250 if (isk) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1251 emit_gri(as, XG_ARITHi(XOg_AND), dest, (int32_t)khash);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1252 emit_rmro(as, XO_MOV, dest, tab, offsetof(GCtab, hmask));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1253 } else if (irt_isstr(kt)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1254 emit_rmro(as, XO_ARITH(XOg_AND), dest, key, offsetof(GCstr, sid));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1255 emit_rmro(as, XO_MOV, dest, tab, offsetof(GCtab, hmask));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1256 } else { /* Must match with hashrot() in lj_tab.c. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1257 emit_rmro(as, XO_ARITH(XOg_AND), dest, tab, offsetof(GCtab, hmask));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1258 emit_rr(as, XO_ARITH(XOg_SUB), dest, tmp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1259 emit_shifti(as, XOg_ROL, tmp, HASH_ROT3);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1260 emit_rr(as, XO_ARITH(XOg_XOR), dest, tmp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1261 emit_shifti(as, XOg_ROL, dest, HASH_ROT2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1262 emit_rr(as, XO_ARITH(XOg_SUB), tmp, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1263 emit_shifti(as, XOg_ROL, dest, HASH_ROT1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1264 emit_rr(as, XO_ARITH(XOg_XOR), tmp, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1265 if (irt_isnum(kt)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1266 emit_rr(as, XO_ARITH(XOg_ADD), dest, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1267 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1268 emit_shifti(as, XOg_SHR\|REX_64, dest, 32);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1269 emit_rr(as, XO_MOV, tmp, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1270 emit_rr(as, XO_MOVDto, key\|REX_64, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1271 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1272 emit_rmro(as, XO_MOV, dest, RID_ESP, ra_spill(as, irkey)+4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1273 emit_rr(as, XO_MOVDto, key, tmp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1274 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1275 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1276 emit_rr(as, XO_MOV, tmp, key);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1277 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1278 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1279 emit_gri(as, XG_ARITHi(XOg_XOR), dest, irt_toitype(kt) << 15);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1280 if ((as->flags & JIT_F_BMI2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1281 emit_i8(as, 32);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1282 emit_mrm(as, XV_RORX\|VEX_64, dest, key);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1283 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1284 emit_shifti(as, XOg_SHR\|REX_64, dest, 32);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1285 emit_rr(as, XO_MOV, dest\|REX_64, key\|REX_64);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1286 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1287 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1288 emit_rmro(as, XO_LEA, dest, key, HASH_BIAS);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1289 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1290 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1291 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1292 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1293 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1294
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1295 static void asm_hrefk(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1296 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1297 IRIns *kslot = IR(ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1298 IRIns *irkey = IR(kslot->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1299 int32_t ofs = (int32_t)(kslot->op2 * sizeof(Node));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1300 Reg dest = ra_used(ir) ? ra_dest(as, ir, RSET_GPR) : RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1301 Reg node = ra_alloc1(as, ir->op1, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1302 #if !LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1303 MCLabel l_exit;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1304 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1305 lj_assertA(ofs % sizeof(Node) == 0, "unaligned HREFK slot");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1306 if (ra_hasreg(dest)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1307 if (ofs != 0) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1308 if (dest == node)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1309 emit_gri(as, XG_ARITHi(XOg_ADD), dest\|REX_GC64, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1310 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1311 emit_rmro(as, XO_LEA, dest\|REX_GC64, node, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1312 } else if (dest != node) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1313 emit_rr(as, XO_MOV, dest\|REX_GC64, node);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1314 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1315 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1316 asm_guardcc(as, CC_NE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1317 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1318 if (!irt_ispri(irkey->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1319 Reg key = ra_scratch(as, rset_exclude(RSET_GPR, node));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1320 emit_rmro(as, XO_CMP, key\|REX_64, node,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1321 ofs + (int32_t)offsetof(Node, key.u64));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1322 lj_assertA(irt_isnum(irkey->t) \|\| irt_isgcv(irkey->t),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1323 "bad HREFK key type");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1324 /* Assumes -0.0 is already canonicalized to +0.0. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1325 emit_loadu64(as, key, irt_isnum(irkey->t) ? ir_knum(irkey)->u64 :
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1326 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1327 ((uint64_t)irt_toitype(irkey->t) << 47) \|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1328 (uint64_t)ir_kgc(irkey));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1329 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1330 ((uint64_t)irt_toitype(irkey->t) << 32) \|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1331 (uint64_t)(uint32_t)ptr2addr(ir_kgc(irkey)));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1332 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1333 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1334 lj_assertA(!irt_isnil(irkey->t), "bad HREFK key type");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1335 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1336 emit_i32(as, (irt_toitype(irkey->t)<<15)\|0x7fff);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1337 emit_rmro(as, XO_ARITHi, XOg_CMP, node,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1338 ofs + (int32_t)offsetof(Node, key.it));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1339 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1340 emit_i8(as, irt_toitype(irkey->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1341 emit_rmro(as, XO_ARITHi8, XOg_CMP, node,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1342 ofs + (int32_t)offsetof(Node, key.it));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1343 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1344 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1345 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1346 l_exit = emit_label(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1347 if (irt_isnum(irkey->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1348 /* Assumes -0.0 is already canonicalized to +0.0. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1349 emit_gmroi(as, XG_ARITHi(XOg_CMP), node,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1350 ofs + (int32_t)offsetof(Node, key.u32.lo),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1351 (int32_t)ir_knum(irkey)->u32.lo);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1352 emit_sjcc(as, CC_NE, l_exit);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1353 emit_gmroi(as, XG_ARITHi(XOg_CMP), node,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1354 ofs + (int32_t)offsetof(Node, key.u32.hi),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1355 (int32_t)ir_knum(irkey)->u32.hi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1356 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1357 if (!irt_ispri(irkey->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1358 lj_assertA(irt_isgcv(irkey->t), "bad HREFK key type");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1359 emit_gmroi(as, XG_ARITHi(XOg_CMP), node,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1360 ofs + (int32_t)offsetof(Node, key.gcr),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1361 ptr2addr(ir_kgc(irkey)));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1362 emit_sjcc(as, CC_NE, l_exit);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1363 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1364 lj_assertA(!irt_isnil(irkey->t), "bad HREFK key type");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1365 emit_i8(as, irt_toitype(irkey->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1366 emit_rmro(as, XO_ARITHi8, XOg_CMP, node,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1367 ofs + (int32_t)offsetof(Node, key.it));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1368 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1369 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1370 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1371
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1372 static void asm_uref(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1373 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1374 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1375 if (irref_isk(ir->op1)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1376 GCfunc *fn = ir_kfunc(IR(ir->op1));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1377 MRef *v = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.v;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1378 emit_rma(as, XO_MOV, dest\|REX_GC64, v);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1379 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1380 Reg uv = ra_scratch(as, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1381 Reg func = ra_alloc1(as, ir->op1, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1382 if (ir->o == IR_UREFC) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1383 emit_rmro(as, XO_LEA, dest\|REX_GC64, uv, offsetof(GCupval, tv));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1384 asm_guardcc(as, CC_NE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1385 emit_i8(as, 1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1386 emit_rmro(as, XO_ARITHib, XOg_CMP, uv, offsetof(GCupval, closed));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1387 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1388 emit_rmro(as, XO_MOV, dest\|REX_GC64, uv, offsetof(GCupval, v));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1389 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1390 emit_rmro(as, XO_MOV, uv\|REX_GC64, func,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1391 (int32_t)offsetof(GCfuncL, uvptr) +
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1392 (int32_t)sizeof(MRef) * (int32_t)(ir->op2 >> 8));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1393 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1394 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1395
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1396 static void asm_fref(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1397 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1398 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1399 asm_fusefref(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1400 emit_mrm(as, XO_LEA, dest, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1401 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1402
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1403 static void asm_strref(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1404 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1405 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1406 asm_fusestrref(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1407 if (as->mrm.base == RID_NONE)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1408 emit_loadi(as, dest, as->mrm.ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1409 else if (as->mrm.base == dest && as->mrm.idx == RID_NONE)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1410 emit_gri(as, XG_ARITHi(XOg_ADD), dest\|REX_GC64, as->mrm.ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1411 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1412 emit_mrm(as, XO_LEA, dest\|REX_GC64, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1413 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1414
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1415 /* -- Loads and stores ---------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1416
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1417 static void asm_fxload(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1418 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1419 Reg dest = ra_dest(as, ir, irt_isfp(ir->t) ? RSET_FPR : RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1420 x86Op xo;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1421 if (ir->o == IR_FLOAD)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1422 asm_fusefref(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1423 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1424 asm_fusexref(as, ir->op1, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1425 /* ir->op2 is ignored -- unaligned loads are ok on x86. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1426 switch (irt_type(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1427 case IRT_I8: xo = XO_MOVSXb; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1428 case IRT_U8: xo = XO_MOVZXb; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1429 case IRT_I16: xo = XO_MOVSXw; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1430 case IRT_U16: xo = XO_MOVZXw; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1431 case IRT_NUM: xo = XO_MOVSD; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1432 case IRT_FLOAT: xo = XO_MOVSS; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1433 default:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1434 if (LJ_64 && irt_is64(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1435 dest \|= REX_64;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1436 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1437 lj_assertA(irt_isint(ir->t) \|\| irt_isu32(ir->t) \|\| irt_isaddr(ir->t),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1438 "unsplit 64 bit load");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1439 xo = XO_MOV;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1440 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1441 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1442 emit_mrm(as, xo, dest, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1443 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1444
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1445 #define asm_fload(as, ir) asm_fxload(as, ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1446 #define asm_xload(as, ir) asm_fxload(as, ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1447
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1448 static void asm_fxstore(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1449 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1450 RegSet allow = RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1451 Reg src = RID_NONE, osrc = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1452 int32_t k = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1453 if (ir->r == RID_SINK)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1454 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1455 /* The IRT_I16/IRT_U16 stores should never be simplified for constant
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1456 ** values since mov word [mem], imm16 has a length-changing prefix.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1457 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1458 if (irt_isi16(ir->t) \|\| irt_isu16(ir->t) \|\| irt_isfp(ir->t) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1459 !asm_isk32(as, ir->op2, &k)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1460 RegSet allow8 = irt_isfp(ir->t) ? RSET_FPR :
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1461 (irt_isi8(ir->t) \|\| irt_isu8(ir->t)) ? RSET_GPR8 : RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1462 src = osrc = ra_alloc1(as, ir->op2, allow8);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1463 if (!LJ_64 && !rset_test(allow8, src)) { /* Already in wrong register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1464 rset_clear(allow, osrc);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1465 src = ra_scratch(as, allow8);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1466 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1467 rset_clear(allow, src);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1468 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1469 if (ir->o == IR_FSTORE) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1470 asm_fusefref(as, IR(ir->op1), allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1471 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1472 asm_fusexref(as, ir->op1, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1473 if (LJ_32 && ir->o == IR_HIOP) as->mrm.ofs += 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1474 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1475 if (ra_hasreg(src)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1476 x86Op xo;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1477 switch (irt_type(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1478 case IRT_I8: case IRT_U8: xo = XO_MOVtob; src \|= FORCE_REX; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1479 case IRT_I16: case IRT_U16: xo = XO_MOVtow; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1480 case IRT_NUM: xo = XO_MOVSDto; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1481 case IRT_FLOAT: xo = XO_MOVSSto; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1482 #if LJ_64 && !LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1483 case IRT_LIGHTUD:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1484 /* NYI: mask 64 bit lightuserdata. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1485 lj_assertA(0, "store of lightuserdata");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1486 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1487 default:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1488 if (LJ_64 && irt_is64(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1489 src \|= REX_64;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1490 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1491 lj_assertA(irt_isint(ir->t) \|\| irt_isu32(ir->t) \|\| irt_isaddr(ir->t),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1492 "unsplit 64 bit store");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1493 xo = XO_MOVto;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1494 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1495 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1496 emit_mrm(as, xo, src, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1497 if (!LJ_64 && src != osrc) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1498 ra_noweak(as, osrc);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1499 emit_rr(as, XO_MOV, src, osrc);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1500 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1501 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1502 if (irt_isi8(ir->t) \|\| irt_isu8(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1503 emit_i8(as, k);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1504 emit_mrm(as, XO_MOVmib, 0, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1505 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1506 lj_assertA(irt_is64(ir->t) \|\| irt_isint(ir->t) \|\| irt_isu32(ir->t) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1507 irt_isaddr(ir->t), "bad store type");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1508 emit_i32(as, k);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1509 emit_mrm(as, XO_MOVmi, REX_64IR(ir, 0), RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1510 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1511 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1512 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1513
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1514 #define asm_fstore(as, ir) asm_fxstore(as, ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1515 #define asm_xstore(as, ir) asm_fxstore(as, ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1516
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1517 #if LJ_64 && !LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1518 static Reg asm_load_lightud64(ASMState as, IRIns ir, int typecheck)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1519 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1520 if (ra_used(ir) \|\| typecheck) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1521 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1522 if (typecheck) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1523 Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, dest));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1524 asm_guardcc(as, CC_NE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1525 emit_i8(as, -2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1526 emit_rr(as, XO_ARITHi8, XOg_CMP, tmp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1527 emit_shifti(as, XOg_SAR\|REX_64, tmp, 47);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1528 emit_rr(as, XO_MOV, tmp\|REX_64, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1529 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1530 return dest;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1531 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1532 return RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1533 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1534 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1535 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1536
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1537 static void asm_ahuvload(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1538 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1539 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1540 Reg tmp = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1541 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1542 lj_assertA(irt_isnum(ir->t) \|\| irt_ispri(ir->t) \|\| irt_isaddr(ir->t) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1543 (LJ_DUALNUM && irt_isint(ir->t)),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1544 "bad load type %d", irt_type(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1545 #if LJ_64 && !LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1546 if (irt_islightud(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1547 Reg dest = asm_load_lightud64(as, ir, 1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1548 if (ra_hasreg(dest)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1549 asm_fuseahuref(as, ir->op1, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1550 if (ir->o == IR_VLOAD) as->mrm.ofs += 8 * ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1551 emit_mrm(as, XO_MOV, dest\|REX_64, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1552 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1553 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1554 } else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1555 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1556 if (ra_used(ir)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1557 RegSet allow = irt_isnum(ir->t) ? RSET_FPR : RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1558 Reg dest = ra_dest(as, ir, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1559 asm_fuseahuref(as, ir->op1, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1560 if (ir->o == IR_VLOAD) as->mrm.ofs += 8 * ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1561 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1562 if (irt_isaddr(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1563 emit_shifti(as, XOg_SHR\|REX_64, dest, 17);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1564 asm_guardcc(as, CC_NE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1565 emit_i8(as, irt_toitype(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1566 emit_rr(as, XO_ARITHi8, XOg_CMP, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1567 emit_i8(as, XI_O16);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1568 if ((as->flags & JIT_F_BMI2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1569 emit_i8(as, 47);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1570 emit_mrm(as, XV_RORX\|VEX_64, dest, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1571 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1572 emit_shifti(as, XOg_ROR\|REX_64, dest, 47);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1573 emit_mrm(as, XO_MOV, dest\|REX_64, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1574 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1575 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1576 } else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1577 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1578 emit_mrm(as, dest < RID_MAX_GPR ? XO_MOV : XO_MOVSD, dest, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1579 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1580 RegSet gpr = RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1581 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1582 if (irt_isaddr(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1583 tmp = ra_scratch(as, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1584 gpr = rset_exclude(gpr, tmp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1585 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1586 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1587 asm_fuseahuref(as, ir->op1, gpr);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1588 if (ir->o == IR_VLOAD) as->mrm.ofs += 8 * ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1589 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1590 /* Always do the type check, even if the load result is unused. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1591 as->mrm.ofs += 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1592 asm_guardcc(as, irt_isnum(ir->t) ? CC_AE : CC_NE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1593 if (LJ_64 && irt_type(ir->t) >= IRT_NUM) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1594 lj_assertA(irt_isinteger(ir->t) \|\| irt_isnum(ir->t),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1595 "bad load type %d", irt_type(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1596 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1597 emit_u32(as, LJ_TISNUM << 15);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1598 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1599 emit_u32(as, LJ_TISNUM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1600 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1601 emit_mrm(as, XO_ARITHi, XOg_CMP, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1602 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1603 } else if (irt_isaddr(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1604 as->mrm.ofs -= 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1605 emit_i8(as, irt_toitype(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1606 emit_mrm(as, XO_ARITHi8, XOg_CMP, tmp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1607 emit_shifti(as, XOg_SAR\|REX_64, tmp, 47);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1608 emit_mrm(as, XO_MOV, tmp\|REX_64, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1609 } else if (irt_isnil(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1610 as->mrm.ofs -= 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1611 emit_i8(as, -1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1612 emit_mrm(as, XO_ARITHi8, XOg_CMP\|REX_64, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1613 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1614 emit_u32(as, (irt_toitype(ir->t) << 15) \| 0x7fff);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1615 emit_mrm(as, XO_ARITHi, XOg_CMP, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1616 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1617 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1618 emit_i8(as, irt_toitype(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1619 emit_mrm(as, XO_ARITHi8, XOg_CMP, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1620 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1621 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1622 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1623
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1624 static void asm_ahustore(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1625 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1626 if (ir->r == RID_SINK)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1627 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1628 if (irt_isnum(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1629 Reg src = ra_alloc1(as, ir->op2, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1630 asm_fuseahuref(as, ir->op1, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1631 emit_mrm(as, XO_MOVSDto, src, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1632 #if LJ_64 && !LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1633 } else if (irt_islightud(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1634 Reg src = ra_alloc1(as, ir->op2, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1635 asm_fuseahuref(as, ir->op1, rset_exclude(RSET_GPR, src));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1636 emit_mrm(as, XO_MOVto, src\|REX_64, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1637 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1638 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1639 } else if (irref_isk(ir->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1640 TValue k;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1641 lj_ir_kvalue(as->J->L, &k, IR(ir->op2));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1642 asm_fuseahuref(as, ir->op1, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1643 if (tvisnil(&k)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1644 emit_i32(as, -1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1645 emit_mrm(as, XO_MOVmi, REX_64, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1646 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1647 emit_u32(as, k.u32.lo);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1648 emit_mrm(as, XO_MOVmi, 0, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1649 as->mrm.ofs += 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1650 emit_u32(as, k.u32.hi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1651 emit_mrm(as, XO_MOVmi, 0, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1652 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1653 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1654 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1655 IRIns *irr = IR(ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1656 RegSet allow = RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1657 Reg src = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1658 if (!irref_isk(ir->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1659 src = ra_alloc1(as, ir->op2, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1660 rset_clear(allow, src);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1661 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1662 asm_fuseahuref(as, ir->op1, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1663 if (ra_hasreg(src)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1664 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1665 if (!(LJ_DUALNUM && irt_isinteger(ir->t))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1666 /* TODO: 64 bit store + 32 bit load-modify-store is suboptimal. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1667 as->mrm.ofs += 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1668 emit_u32(as, irt_toitype(ir->t) << 15);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1669 emit_mrm(as, XO_ARITHi, XOg_OR, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1670 as->mrm.ofs -= 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1671 emit_mrm(as, XO_MOVto, src\|REX_64, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1672 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1673 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1674 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1675 emit_mrm(as, XO_MOVto, src, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1676 } else if (!irt_ispri(irr->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1677 lj_assertA(irt_isaddr(ir->t) \|\| (LJ_DUALNUM && irt_isinteger(ir->t)),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1678 "bad store type");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1679 emit_i32(as, irr->i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1680 emit_mrm(as, XO_MOVmi, 0, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1681 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1682 as->mrm.ofs += 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1683 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1684 lj_assertA(LJ_DUALNUM && irt_isinteger(ir->t), "bad store type");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1685 emit_i32(as, LJ_TNUMX << 15);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1686 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1687 emit_i32(as, (int32_t)irt_toitype(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1688 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1689 emit_mrm(as, XO_MOVmi, 0, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1690 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1691 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1692
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1693 static void asm_sload(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1694 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1695 int32_t ofs = 8*((int32_t)ir->op1-1-LJ_FR2) +
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1696 (!LJ_FR2 && (ir->op2 & IRSLOAD_FRAME) ? 4 : 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1697 IRType1 t = ir->t;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1698 Reg base;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1699 lj_assertA(!(ir->op2 & IRSLOAD_PARENT),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1700 "bad parent SLOAD"); /* Handled by asm_head_side(). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1701 lj_assertA(irt_isguard(t) \|\| !(ir->op2 & IRSLOAD_TYPECHECK),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1702 "inconsistent SLOAD variant");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1703 lj_assertA(LJ_DUALNUM \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1704 !irt_isint(t) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1705 (ir->op2 & (IRSLOAD_CONVERT\|IRSLOAD_FRAME\|IRSLOAD_KEYINDEX)),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1706 "bad SLOAD type");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1707 if ((ir->op2 & IRSLOAD_CONVERT) && irt_isguard(t) && irt_isint(t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1708 Reg left = ra_scratch(as, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1709 asm_tointg(as, ir, left); /* Frees dest reg. Do this before base alloc. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1710 base = ra_alloc1(as, REF_BASE, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1711 emit_rmro(as, XO_MOVSD, left, base, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1712 t.irt = IRT_NUM; /* Continue with a regular number type check. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1713 #if LJ_64 && !LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1714 } else if (irt_islightud(t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1715 Reg dest = asm_load_lightud64(as, ir, (ir->op2 & IRSLOAD_TYPECHECK));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1716 if (ra_hasreg(dest)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1717 base = ra_alloc1(as, REF_BASE, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1718 emit_rmro(as, XO_MOV, dest\|REX_64, base, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1719 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1720 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1721 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1722 } else if (ra_used(ir)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1723 RegSet allow = irt_isnum(t) ? RSET_FPR : RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1724 Reg dest = ra_dest(as, ir, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1725 base = ra_alloc1(as, REF_BASE, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1726 lj_assertA(irt_isnum(t) \|\| irt_isint(t) \|\| irt_isaddr(t),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1727 "bad SLOAD type %d", irt_type(t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1728 if ((ir->op2 & IRSLOAD_CONVERT)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1729 t.irt = irt_isint(t) ? IRT_NUM : IRT_INT; /* Check for original type. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1730 emit_rmro(as, irt_isint(t) ? XO_CVTSI2SD : XO_CVTTSD2SI, dest, base, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1731 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1732 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1733 if (irt_isaddr(t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1734 /* LJ_GC64 type check + tag removal without BMI2 and with BMI2:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1735 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1736 ** mov r64, [addr] rorx r64, [addr], 47
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1737 ** ror r64, 47
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1738 ** cmp r16, itype cmp r16, itype
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1739 ** jne ->exit jne ->exit
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1740 ** shr r64, 16 shr r64, 16
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1741 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1742 emit_shifti(as, XOg_SHR\|REX_64, dest, 17);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1743 if ((ir->op2 & IRSLOAD_TYPECHECK)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1744 asm_guardcc(as, CC_NE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1745 emit_i8(as, irt_toitype(t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1746 emit_rr(as, XO_ARITHi8, XOg_CMP, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1747 emit_i8(as, XI_O16);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1748 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1749 if ((as->flags & JIT_F_BMI2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1750 emit_i8(as, 47);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1751 emit_rmro(as, XV_RORX\|VEX_64, dest, base, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1752 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1753 if ((ir->op2 & IRSLOAD_TYPECHECK))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1754 emit_shifti(as, XOg_ROR\|REX_64, dest, 47);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1755 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1756 emit_shifti(as, XOg_SHL\|REX_64, dest, 17);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1757 emit_rmro(as, XO_MOV, dest\|REX_64, base, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1758 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1759 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1760 } else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1761 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1762 emit_rmro(as, irt_isnum(t) ? XO_MOVSD : XO_MOV, dest, base, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1763 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1764 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1765 if (!(ir->op2 & IRSLOAD_TYPECHECK))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1766 return; /* No type check: avoid base alloc. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1767 base = ra_alloc1(as, REF_BASE, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1768 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1769 if ((ir->op2 & IRSLOAD_TYPECHECK)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1770 /* Need type check, even if the load result is unused. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1771 asm_guardcc(as, irt_isnum(t) ? CC_AE : CC_NE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1772 if ((LJ_64 && irt_type(t) >= IRT_NUM) \|\| (ir->op2 & IRSLOAD_KEYINDEX)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1773 lj_assertA(irt_isinteger(t) \|\| irt_isnum(t),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1774 "bad SLOAD type %d", irt_type(t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1775 emit_u32(as, (ir->op2 & IRSLOAD_KEYINDEX) ? LJ_KEYINDEX :
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1776 LJ_GC64 ? (LJ_TISNUM << 15) : LJ_TISNUM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1777 emit_rmro(as, XO_ARITHi, XOg_CMP, base, ofs+4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1778 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1779 } else if (irt_isnil(t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1780 /* LJ_GC64 type check for nil:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1781 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1782 ** cmp qword [addr], -1
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1783 ** jne ->exit
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1784 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1785 emit_i8(as, -1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1786 emit_rmro(as, XO_ARITHi8, XOg_CMP\|REX_64, base, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1787 } else if (irt_ispri(t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1788 emit_u32(as, (irt_toitype(t) << 15) \| 0x7fff);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1789 emit_rmro(as, XO_ARITHi, XOg_CMP, base, ofs+4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1790 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1791 /* LJ_GC64 type check only:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1792 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1793 ** mov r64, [addr]
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1794 ** sar r64, 47
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1795 ** cmp r32, itype
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1796 ** jne ->exit
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1797 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1798 Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, base));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1799 emit_i8(as, irt_toitype(t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1800 emit_rr(as, XO_ARITHi8, XOg_CMP, tmp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1801 emit_shifti(as, XOg_SAR\|REX_64, tmp, 47);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1802 emit_rmro(as, XO_MOV, tmp\|REX_64, base, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1803 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1804 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1805 emit_i8(as, irt_toitype(t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1806 emit_rmro(as, XO_ARITHi8, XOg_CMP, base, ofs+4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1807 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1808 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1809 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1810 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1811
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1812 /* -- Allocations --------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1813
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1814 #if LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1815 static void asm_cnew(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1816 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1817 CTState *cts = ctype_ctsG(J2G(as->J));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1818 CTypeID id = (CTypeID)IR(ir->op1)->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1819 CTSize sz;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1820 CTInfo info = lj_ctype_info(cts, id, &sz);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1821 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_mem_newgco];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1822 IRRef args[4];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1823 lj_assertA(sz != CTSIZE_INVALID \|\| (ir->o == IR_CNEW && ir->op2 != REF_NIL),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1824 "bad CNEW/CNEWI operands");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1825
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1826 as->gcsteps++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1827 asm_setupresult(as, ir, ci); /* GCcdata * */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1828
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1829 /* Initialize immutable cdata object. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1830 if (ir->o == IR_CNEWI) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1831 RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1832 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1833 Reg r64 = sz == 8 ? REX_64 : 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1834 if (irref_isk(ir->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1835 IRIns *irk = IR(ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1836 uint64_t k = (irk->o == IR_KINT64 \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1837 (LJ_GC64 && (irk->o == IR_KPTR \|\| irk->o == IR_KKPTR))) ?
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1838 ir_k64(irk)->u64 : (uint64_t)(uint32_t)irk->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1839 if (sz == 4 \|\| checki32((int64_t)k)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1840 emit_i32(as, (int32_t)k);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1841 emit_rmro(as, XO_MOVmi, r64, RID_RET, sizeof(GCcdata));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1842 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1843 emit_movtomro(as, RID_ECX + r64, RID_RET, sizeof(GCcdata));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1844 emit_loadu64(as, RID_ECX, k);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1845 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1846 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1847 Reg r = ra_alloc1(as, ir->op2, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1848 emit_movtomro(as, r + r64, RID_RET, sizeof(GCcdata));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1849 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1850 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1851 int32_t ofs = sizeof(GCcdata);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1852 if (sz == 8) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1853 ofs += 4; ir++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1854 lj_assertA(ir->o == IR_HIOP, "missing CNEWI HIOP");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1855 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1856 do {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1857 if (irref_isk(ir->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1858 emit_movmroi(as, RID_RET, ofs, IR(ir->op2)->i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1859 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1860 Reg r = ra_alloc1(as, ir->op2, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1861 emit_movtomro(as, r, RID_RET, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1862 rset_clear(allow, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1863 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1864 if (ofs == sizeof(GCcdata)) break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1865 ofs -= 4; ir--;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1866 } while (1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1867 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1868 lj_assertA(sz == 4 \|\| sz == 8, "bad CNEWI size %d", sz);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1869 } else if (ir->op2 != REF_NIL) { /* Create VLA/VLS/aligned cdata. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1870 ci = &lj_ir_callinfo[IRCALL_lj_cdata_newv];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1871 args[0] = ASMREF_L; /* lua_State L /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1872 args[1] = ir->op1; /* CTypeID id */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1873 args[2] = ir->op2; /* CTSize sz */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1874 args[3] = ASMREF_TMP1; /* CTSize align */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1875 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1876 emit_loadi(as, ra_releasetmp(as, ASMREF_TMP1), (int32_t)ctype_align(info));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1877 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1878 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1879
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1880 /* Combine initialization of marked, gct and ctypeid. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1881 emit_movtomro(as, RID_ECX, RID_RET, offsetof(GCcdata, marked));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1882 emit_gri(as, XG_ARITHi(XOg_OR), RID_ECX,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1883 (int32_t)((~LJ_TCDATA<<8)+(id<<16)));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1884 emit_gri(as, XG_ARITHi(XOg_AND), RID_ECX, LJ_GC_WHITES);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1885 emit_opgl(as, XO_MOVZXb, RID_ECX, gc.currentwhite);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1886
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1887 args[0] = ASMREF_L; /* lua_State L /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1888 args[1] = ASMREF_TMP1; /* MSize size */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1889 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1890 emit_loadi(as, ra_releasetmp(as, ASMREF_TMP1), (int32_t)(sz+sizeof(GCcdata)));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1891 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1892 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1893
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1894 /* -- Write barriers ------------------------------------------------------ */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1895
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1896 static void asm_tbar(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1897 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1898 Reg tab = ra_alloc1(as, ir->op1, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1899 Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, tab));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1900 MCLabel l_end = emit_label(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1901 emit_movtomro(as, tmp\|REX_GC64, tab, offsetof(GCtab, gclist));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1902 emit_setgl(as, tab, gc.grayagain);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1903 emit_getgl(as, tmp, gc.grayagain);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1904 emit_i8(as, ~LJ_GC_BLACK);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1905 emit_rmro(as, XO_ARITHib, XOg_AND, tab, offsetof(GCtab, marked));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1906 emit_sjcc(as, CC_Z, l_end);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1907 emit_i8(as, LJ_GC_BLACK);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1908 emit_rmro(as, XO_GROUP3b, XOg_TEST, tab, offsetof(GCtab, marked));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1909 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1910
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1911 static void asm_obar(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1912 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1913 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_barrieruv];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1914 IRRef args[2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1915 MCLabel l_end;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1916 Reg obj;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1917 /* No need for other object barriers (yet). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1918 lj_assertA(IR(ir->op1)->o == IR_UREFC, "bad OBAR type");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1919 ra_evictset(as, RSET_SCRATCH);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1920 l_end = emit_label(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1921 args[0] = ASMREF_TMP1; /* global_State g /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1922 args[1] = ir->op1; /* TValue tv /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1923 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1924 emit_loada(as, ra_releasetmp(as, ASMREF_TMP1), J2G(as->J));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1925 obj = IR(ir->op1)->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1926 emit_sjcc(as, CC_Z, l_end);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1927 emit_i8(as, LJ_GC_WHITES);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1928 if (irref_isk(ir->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1929 GCobj *vp = ir_kgc(IR(ir->op2));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1930 emit_rma(as, XO_GROUP3b, XOg_TEST, &vp->gch.marked);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1931 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1932 Reg val = ra_alloc1(as, ir->op2, rset_exclude(RSET_SCRATCH&RSET_GPR, obj));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1933 emit_rmro(as, XO_GROUP3b, XOg_TEST, val, (int32_t)offsetof(GChead, marked));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1934 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1935 emit_sjcc(as, CC_Z, l_end);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1936 emit_i8(as, LJ_GC_BLACK);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1937 emit_rmro(as, XO_GROUP3b, XOg_TEST, obj,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1938 (int32_t)offsetof(GCupval, marked)-(int32_t)offsetof(GCupval, tv));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1939 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1940
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1941 /* -- FP/int arithmetic and logic operations ------------------------------ */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1942
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1943 /* Load reference onto x87 stack. Force a spill to memory if needed. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1944 static void asm_x87load(ASMState *as, IRRef ref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1945 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1946 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1947 if (ir->o == IR_KNUM) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1948 cTValue *tv = ir_knum(ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1949 if (tvispzero(tv)) /* Use fldz only for +0. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1950 emit_x87op(as, XI_FLDZ);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1951 else if (tvispone(tv))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1952 emit_x87op(as, XI_FLD1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1953 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1954 emit_rma(as, XO_FLDq, XOg_FLDq, tv);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1955 } else if (ir->o == IR_CONV && ir->op2 == IRCONV_NUM_INT && !ra_used(ir) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1956 !irref_isk(ir->op1) && mayfuse(as, ir->op1)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1957 IRIns *iri = IR(ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1958 emit_rmro(as, XO_FILDd, XOg_FILDd, RID_ESP, ra_spill(as, iri));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1959 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1960 emit_mrm(as, XO_FLDq, XOg_FLDq, asm_fuseload(as, ref, RSET_EMPTY));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1961 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1962 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1963
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1964 static void asm_fpmath(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1965 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1966 IRFPMathOp fpm = (IRFPMathOp)ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1967 if (fpm == IRFPM_SQRT) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1968 Reg dest = ra_dest(as, ir, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1969 Reg left = asm_fuseload(as, ir->op1, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1970 emit_mrm(as, XO_SQRTSD, dest, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1971 } else if (fpm <= IRFPM_TRUNC) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1972 if (as->flags & JIT_F_SSE4_1) { /* SSE4.1 has a rounding instruction. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1973 Reg dest = ra_dest(as, ir, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1974 Reg left = asm_fuseload(as, ir->op1, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1975 /* ROUNDSD has a 4-byte opcode which doesn't fit in x86Op.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1976 ** Let's pretend it's a 3-byte opcode, and compensate afterwards.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1977 ** This is atrocious, but the alternatives are much worse.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1978 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1979 /* Round down/up/trunc == 1001/1010/1011. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1980 emit_i8(as, 0x09 + fpm);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1981 emit_mrm(as, XO_ROUNDSD, dest, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1982 if (LJ_64 && as->mcp[1] != (MCode)(XO_ROUNDSD >> 16)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1983 as->mcp[0] = as->mcp[1]; as->mcp[1] = 0x0f; /* Swap 0F and REX. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1984 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1985 --as->mcp = 0x66; / 1st byte of ROUNDSD opcode. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1986 } else { /* Call helper functions for SSE2 variant. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1987 /* The modified regs must match with the .dasc implementation. /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1988 RegSet drop = RSET_RANGE(RID_XMM0, RID_XMM3+1)\|RID2RSET(RID_EAX);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1989 if (ra_hasreg(ir->r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1990 rset_clear(drop, ir->r); /* Dest reg handled below. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1991 ra_evictset(as, drop);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1992 ra_destreg(as, ir, RID_XMM0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1993 emit_call(as, fpm == IRFPM_FLOOR ? lj_vm_floor_sse :
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1994 fpm == IRFPM_CEIL ? lj_vm_ceil_sse : lj_vm_trunc_sse);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1995 ra_left(as, RID_XMM0, ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1996 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1997 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1998 asm_callid(as, ir, IRCALL_lj_vm_floor + fpm);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1999 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2000 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2001
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2002 static void asm_ldexp(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2003 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2004 int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2005 Reg dest = ir->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2006 if (ra_hasreg(dest)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2007 ra_free(as, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2008 ra_modified(as, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2009 emit_rmro(as, XO_MOVSD, dest, RID_ESP, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2010 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2011 emit_rmro(as, XO_FSTPq, XOg_FSTPq, RID_ESP, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2012 emit_x87op(as, XI_FPOP1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2013 emit_x87op(as, XI_FSCALE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2014 asm_x87load(as, ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2015 asm_x87load(as, ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2016 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2017
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2018 static int asm_swapops(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2019 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2020 IRIns *irl = IR(ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2021 IRIns *irr = IR(ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2022 lj_assertA(ra_noreg(irr->r), "bad usage");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2023 if (!irm_iscomm(lj_ir_mode[ir->o]))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2024 return 0; /* Can't swap non-commutative operations. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2025 if (irref_isk(ir->op2))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2026 return 0; /* Don't swap constants to the left. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2027 if (ra_hasreg(irl->r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2028 return 1; /* Swap if left already has a register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2029 if (ra_samehint(ir->r, irr->r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2030 return 1; /* Swap if dest and right have matching hints. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2031 if (as->curins > as->loopref) { /* In variant part? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2032 if (ir->op2 < as->loopref && !irt_isphi(irr->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2033 return 0; /* Keep invariants on the right. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2034 if (ir->op1 < as->loopref && !irt_isphi(irl->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2035 return 1; /* Swap invariants to the right. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2036 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2037 if (opisfusableload(irl->o))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2038 return 1; /* Swap fusable loads to the right. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2039 return 0; /* Otherwise don't swap. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2040 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2041
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2042 static void asm_fparith(ASMState as, IRIns ir, x86Op xo)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2043 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2044 IRRef lref = ir->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2045 IRRef rref = ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2046 RegSet allow = RSET_FPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2047 Reg dest;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2048 Reg right = IR(rref)->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2049 if (ra_hasreg(right)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2050 rset_clear(allow, right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2051 ra_noweak(as, right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2052 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2053 dest = ra_dest(as, ir, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2054 if (lref == rref) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2055 right = dest;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2056 } else if (ra_noreg(right)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2057 if (asm_swapops(as, ir)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2058 IRRef tmp = lref; lref = rref; rref = tmp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2059 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2060 right = asm_fuseload(as, rref, rset_clear(allow, dest));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2061 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2062 emit_mrm(as, xo, dest, right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2063 ra_left(as, dest, lref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2064 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2065
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2066 static void asm_intarith(ASMState as, IRIns ir, x86Arith xa)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2067 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2068 IRRef lref = ir->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2069 IRRef rref = ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2070 RegSet allow = RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2071 Reg dest, right;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2072 int32_t k = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2073 if (as->flagmcp == as->mcp) { /* Drop test r,r instruction. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2074 MCode p = as->mcp + ((LJ_64 && as->mcp < XI_TESTb) ? 3 : 2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2075 MCode *q = p[0] == 0x0f ? p+1 : p;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2076 if ((*q & 15) < 14) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2077 if ((q & 15) >= 12) q -= 4; /* L <->S, NL <-> NS */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2078 as->flagmcp = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2079 as->mcp = p;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2080 } /* else: cannot transform LE/NLE to cc without use of OF. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2081 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2082 right = IR(rref)->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2083 if (ra_hasreg(right)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2084 rset_clear(allow, right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2085 ra_noweak(as, right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2086 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2087 dest = ra_dest(as, ir, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2088 if (lref == rref) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2089 right = dest;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2090 } else if (ra_noreg(right) && !asm_isk32(as, rref, &k)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2091 if (asm_swapops(as, ir)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2092 IRRef tmp = lref; lref = rref; rref = tmp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2093 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2094 right = asm_fuseloadm(as, rref, rset_clear(allow, dest), irt_is64(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2095 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2096 if (irt_isguard(ir->t)) /* For IR_ADDOV etc. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2097 asm_guardcc(as, CC_O);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2098 if (xa != XOg_X_IMUL) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2099 if (ra_hasreg(right))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2100 emit_mrm(as, XO_ARITH(xa), REX_64IR(ir, dest), right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2101 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2102 emit_gri(as, XG_ARITHi(xa), REX_64IR(ir, dest), k);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2103 } else if (ra_hasreg(right)) { /* IMUL r, mrm. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2104 emit_mrm(as, XO_IMUL, REX_64IR(ir, dest), right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2105 } else { /* IMUL r, r, k. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2106 /* NYI: use lea/shl/add/sub (FOLD only does 2^k) depending on CPU. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2107 Reg left = asm_fuseloadm(as, lref, RSET_GPR, irt_is64(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2108 x86Op xo;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2109 if (checki8(k)) { emit_i8(as, k); xo = XO_IMULi8;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2110 } else { emit_i32(as, k); xo = XO_IMULi; }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2111 emit_mrm(as, xo, REX_64IR(ir, dest), left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2112 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2113 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2114 ra_left(as, dest, lref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2115 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2116
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2117 /* LEA is really a 4-operand ADD with an independent destination register,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2118 ** up to two source registers and an immediate. One register can be scaled
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2119 ** by 1, 2, 4 or 8. This can be used to avoid moves or to fuse several
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2120 ** instructions.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2121 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2122 ** Currently only a few common cases are supported:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2123 ** - 3-operand ADD: y = a+b; y = a+k with a and b already allocated
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2124 ** - Left ADD fusion: y = (a+b)+k; y = (a+k)+b
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2125 ** - Right ADD fusion: y = a+(b+k)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2126 ** The ommited variants have already been reduced by FOLD.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2127 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2128 ** There are more fusion opportunities, like gathering shifts or joining
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2129 ** common references. But these are probably not worth the trouble, since
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2130 ** array indexing is not decomposed and already makes use of all fields
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2131 ** of the ModRM operand.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2132 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2133 static int asm_lea(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2134 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2135 IRIns *irl = IR(ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2136 IRIns *irr = IR(ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2137 RegSet allow = RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2138 Reg dest;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2139 as->mrm.base = as->mrm.idx = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2140 as->mrm.scale = XM_SCALE1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2141 as->mrm.ofs = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2142 if (ra_hasreg(irl->r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2143 rset_clear(allow, irl->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2144 ra_noweak(as, irl->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2145 as->mrm.base = irl->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2146 if (irref_isk(ir->op2) \|\| ra_hasreg(irr->r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2147 /* The PHI renaming logic does a better job in some cases. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2148 if (ra_hasreg(ir->r) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2149 ((irt_isphi(irl->t) && as->phireg[ir->r] == ir->op1) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2150 (irt_isphi(irr->t) && as->phireg[ir->r] == ir->op2)))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2151 return 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2152 if (irref_isk(ir->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2153 as->mrm.ofs = irr->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2154 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2155 rset_clear(allow, irr->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2156 ra_noweak(as, irr->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2157 as->mrm.idx = irr->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2158 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2159 } else if (irr->o == IR_ADD && mayfuse(as, ir->op2) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2160 irref_isk(irr->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2161 Reg idx = ra_alloc1(as, irr->op1, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2162 rset_clear(allow, idx);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2163 as->mrm.idx = (uint8_t)idx;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2164 as->mrm.ofs = IR(irr->op2)->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2165 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2166 return 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2167 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2168 } else if (ir->op1 != ir->op2 && irl->o == IR_ADD && mayfuse(as, ir->op1) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2169 (irref_isk(ir->op2) \|\| irref_isk(irl->op2))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2170 Reg idx, base = ra_alloc1(as, irl->op1, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2171 rset_clear(allow, base);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2172 as->mrm.base = (uint8_t)base;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2173 if (irref_isk(ir->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2174 as->mrm.ofs = irr->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2175 idx = ra_alloc1(as, irl->op2, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2176 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2177 as->mrm.ofs = IR(irl->op2)->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2178 idx = ra_alloc1(as, ir->op2, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2179 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2180 rset_clear(allow, idx);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2181 as->mrm.idx = (uint8_t)idx;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2182 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2183 return 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2184 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2185 dest = ra_dest(as, ir, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2186 emit_mrm(as, XO_LEA, dest, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2187 return 1; /* Success. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2188 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2189
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2190 static void asm_add(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2191 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2192 if (irt_isnum(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2193 asm_fparith(as, ir, XO_ADDSD);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2194 else if (as->flagmcp == as->mcp \|\| irt_is64(ir->t) \|\| !asm_lea(as, ir))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2195 asm_intarith(as, ir, XOg_ADD);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2196 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2197
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2198 static void asm_sub(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2199 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2200 if (irt_isnum(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2201 asm_fparith(as, ir, XO_SUBSD);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2202 else /* Note: no need for LEA trick here. i-k is encoded as i+(-k). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2203 asm_intarith(as, ir, XOg_SUB);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2204 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2205
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2206 static void asm_mul(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2207 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2208 if (irt_isnum(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2209 asm_fparith(as, ir, XO_MULSD);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2210 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2211 asm_intarith(as, ir, XOg_X_IMUL);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2212 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2213
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2214 #define asm_fpdiv(as, ir) asm_fparith(as, ir, XO_DIVSD)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2215
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2216 static void asm_neg_not(ASMState as, IRIns ir, x86Group3 xg)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2217 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2218 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2219 emit_rr(as, XO_GROUP3, REX_64IR(ir, xg), dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2220 ra_left(as, dest, ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2221 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2222
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2223 static void asm_neg(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2224 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2225 if (irt_isnum(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2226 asm_fparith(as, ir, XO_XORPS);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2227 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2228 asm_neg_not(as, ir, XOg_NEG);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2229 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2230
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2231 #define asm_abs(as, ir) asm_fparith(as, ir, XO_ANDPS)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2232
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2233 static void asm_intmin_max(ASMState as, IRIns ir, int cc)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2234 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2235 Reg right, dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2236 IRRef lref = ir->op1, rref = ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2237 if (irref_isk(rref)) { lref = rref; rref = ir->op1; }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2238 right = ra_alloc1(as, rref, rset_exclude(RSET_GPR, dest));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2239 emit_rr(as, XO_CMOV + (cc<<24), REX_64IR(ir, dest), right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2240 emit_rr(as, XO_CMP, REX_64IR(ir, dest), right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2241 ra_left(as, dest, lref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2242 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2243
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2244 static void asm_min(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2245 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2246 if (irt_isnum(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2247 asm_fparith(as, ir, XO_MINSD);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2248 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2249 asm_intmin_max(as, ir, CC_G);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2250 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2251
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2252 static void asm_max(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2253 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2254 if (irt_isnum(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2255 asm_fparith(as, ir, XO_MAXSD);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2256 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2257 asm_intmin_max(as, ir, CC_L);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2258 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2259
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2260 /* Note: don't use LEA for overflow-checking arithmetic! */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2261 #define asm_addov(as, ir) asm_intarith(as, ir, XOg_ADD)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2262 #define asm_subov(as, ir) asm_intarith(as, ir, XOg_SUB)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2263 #define asm_mulov(as, ir) asm_intarith(as, ir, XOg_X_IMUL)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2264
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2265 #define asm_bnot(as, ir) asm_neg_not(as, ir, XOg_NOT)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2266
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2267 static void asm_bswap(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2268 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2269 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2270 as->mcp = emit_op(XO_BSWAP + ((dest&7) << 24),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2271 REX_64IR(ir, 0), dest, 0, as->mcp, 1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2272 ra_left(as, dest, ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2273 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2274
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2275 #define asm_band(as, ir) asm_intarith(as, ir, XOg_AND)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2276 #define asm_bor(as, ir) asm_intarith(as, ir, XOg_OR)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2277 #define asm_bxor(as, ir) asm_intarith(as, ir, XOg_XOR)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2278
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2279 static void asm_bitshift(ASMState as, IRIns ir, x86Shift xs, x86Op xv)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2280 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2281 IRRef rref = ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2282 IRIns *irr = IR(rref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2283 Reg dest;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2284 if (irref_isk(rref)) { /* Constant shifts. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2285 int shift;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2286 dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2287 shift = irr->i & (irt_is64(ir->t) ? 63 : 31);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2288 if (!xv && shift && (as->flags & JIT_F_BMI2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2289 Reg left = asm_fuseloadm(as, ir->op1, RSET_GPR, irt_is64(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2290 if (left != dest) { /* BMI2 rotate right by constant. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2291 emit_i8(as, xs == XOg_ROL ? -shift : shift);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2292 emit_mrm(as, VEX_64IR(ir, XV_RORX), dest, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2293 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2294 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2295 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2296 switch (shift) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2297 case 0: break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2298 case 1: emit_rr(as, XO_SHIFT1, REX_64IR(ir, xs), dest); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2299 default: emit_shifti(as, REX_64IR(ir, xs), dest, shift); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2300 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2301 } else if ((as->flags & JIT_F_BMI2) && xv) { /* BMI2 variable shifts. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2302 Reg left, right;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2303 dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2304 right = ra_alloc1(as, rref, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2305 left = asm_fuseloadm(as, ir->op1, rset_exclude(RSET_GPR, right),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2306 irt_is64(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2307 emit_mrm(as, VEX_64IR(ir, xv) ^ (right << 19), dest, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2308 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2309 } else { /* Variable shifts implicitly use register cl (i.e. ecx). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2310 Reg right;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2311 dest = ra_dest(as, ir, rset_exclude(RSET_GPR, RID_ECX));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2312 if (dest == RID_ECX) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2313 dest = ra_scratch(as, rset_exclude(RSET_GPR, RID_ECX));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2314 emit_rr(as, XO_MOV, REX_64IR(ir, RID_ECX), dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2315 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2316 right = irr->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2317 if (ra_noreg(right))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2318 right = ra_allocref(as, rref, RID2RSET(RID_ECX));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2319 else if (right != RID_ECX)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2320 ra_scratch(as, RID2RSET(RID_ECX));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2321 emit_rr(as, XO_SHIFTcl, REX_64IR(ir, xs), dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2322 ra_noweak(as, right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2323 if (right != RID_ECX)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2324 emit_rr(as, XO_MOV, RID_ECX, right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2325 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2326 ra_left(as, dest, ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2327 /*
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2328 ** Note: avoid using the flags resulting from a shift or rotate!
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2329 ** All of them cause a partial flag stall, except for r,1 shifts
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2330 ** (but not rotates). And a shift count of 0 leaves the flags unmodified.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2331 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2332 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2333
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2334 #define asm_bshl(as, ir) asm_bitshift(as, ir, XOg_SHL, XV_SHLX)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2335 #define asm_bshr(as, ir) asm_bitshift(as, ir, XOg_SHR, XV_SHRX)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2336 #define asm_bsar(as, ir) asm_bitshift(as, ir, XOg_SAR, XV_SARX)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2337 #define asm_brol(as, ir) asm_bitshift(as, ir, XOg_ROL, 0)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2338 #define asm_bror(as, ir) asm_bitshift(as, ir, XOg_ROR, 0)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2339
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2340 /* -- Comparisons --------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2341
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2342 /* Virtual flags for unordered FP comparisons. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2343 #define VCC_U 0x1000 /* Unordered. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2344 #define VCC_P 0x2000 /* Needs extra CC_P branch. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2345 #define VCC_S 0x4000 /* Swap avoids CC_P branch. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2346 #define VCC_PS (VCC_P\|VCC_S)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2347
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2348 /* Map of comparisons to flags. ORDER IR. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2349 #define COMPFLAGS(ci, cin, cu, cf) ((ci)+((cu)<<4)+((cin)<<8)+(cf))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2350 static const uint16_t asm_compmap[IR_ABC+1] = {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2351 /* signed non-eq unsigned flags */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2352 /* LT */ COMPFLAGS(CC_GE, CC_G, CC_AE, VCC_PS),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2353 /* GE */ COMPFLAGS(CC_L, CC_L, CC_B, 0),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2354 /* LE */ COMPFLAGS(CC_G, CC_G, CC_A, VCC_PS),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2355 /* GT */ COMPFLAGS(CC_LE, CC_L, CC_BE, 0),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2356 /* ULT */ COMPFLAGS(CC_AE, CC_A, CC_AE, VCC_U),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2357 /* UGE */ COMPFLAGS(CC_B, CC_B, CC_B, VCC_U\|VCC_PS),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2358 /* ULE */ COMPFLAGS(CC_A, CC_A, CC_A, VCC_U),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2359 /* UGT */ COMPFLAGS(CC_BE, CC_B, CC_BE, VCC_U\|VCC_PS),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2360 /* EQ */ COMPFLAGS(CC_NE, CC_NE, CC_NE, VCC_P),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2361 /* NE */ COMPFLAGS(CC_E, CC_E, CC_E, VCC_U\|VCC_P),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2362 /* ABC / COMPFLAGS(CC_BE, CC_B, CC_BE, VCC_U\|VCC_PS) / Same as UGT. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2363 };
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2364
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2365 /* FP and integer comparisons. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2366 static void asm_comp(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2367 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2368 uint32_t cc = asm_compmap[ir->o];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2369 if (irt_isnum(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2370 IRRef lref = ir->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2371 IRRef rref = ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2372 Reg left, right;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2373 MCLabel l_around;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2374 /*
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2375 ** An extra CC_P branch is required to preserve ordered/unordered
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2376 ** semantics for FP comparisons. This can be avoided by swapping
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2377 ** the operands and inverting the condition (except for EQ and UNE).
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2378 ** So always try to swap if possible.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2379 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2380 ** Another option would be to swap operands to achieve better memory
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2381 ** operand fusion. But it's unlikely that this outweighs the cost
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2382 ** of the extra branches.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2383 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2384 if (cc & VCC_S) { /* Swap? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2385 IRRef tmp = lref; lref = rref; rref = tmp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2386 cc ^= (VCC_PS\|(5<<4)); /* A <-> B, AE <-> BE, PS <-> none */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2387 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2388 left = ra_alloc1(as, lref, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2389 l_around = emit_label(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2390 asm_guardcc(as, cc >> 4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2391 if (cc & VCC_P) { /* Extra CC_P branch required? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2392 if (!(cc & VCC_U)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2393 asm_guardcc(as, CC_P); /* Branch to exit for ordered comparisons. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2394 } else if (l_around != as->invmcp) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2395 emit_sjcc(as, CC_P, l_around); /* Branch around for unordered. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2396 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2397 /* Patched to mcloop by asm_loop_fixup. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2398 as->loopinv = 2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2399 if (as->realign)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2400 emit_sjcc(as, CC_P, as->mcp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2401 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2402 emit_jcc(as, CC_P, as->mcp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2403 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2404 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2405 right = asm_fuseload(as, rref, rset_exclude(RSET_FPR, left));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2406 emit_mrm(as, XO_UCOMISD, left, right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2407 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2408 IRRef lref = ir->op1, rref = ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2409 IROp leftop = (IROp)(IR(lref)->o);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2410 Reg r64 = REX_64IR(ir, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2411 int32_t imm = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2412 lj_assertA(irt_is64(ir->t) \|\| irt_isint(ir->t) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2413 irt_isu32(ir->t) \|\| irt_isaddr(ir->t) \|\| irt_isu8(ir->t),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2414 "bad comparison data type %d", irt_type(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2415 /* Swap constants (only for ABC) and fusable loads to the right. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2416 if (irref_isk(lref) \|\| (!irref_isk(rref) && opisfusableload(leftop))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2417 if ((cc & 0xc) == 0xc) cc ^= 0x53; /* L <-> G, LE <-> GE */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2418 else if ((cc & 0xa) == 0x2) cc ^= 0x55; /* A <-> B, AE <-> BE */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2419 lref = ir->op2; rref = ir->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2420 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2421 if (asm_isk32(as, rref, &imm)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2422 IRIns *irl = IR(lref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2423 /* Check wether we can use test ins. Not for unsigned, since CF=0. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2424 int usetest = (imm == 0 && (cc & 0xa) != 0x2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2425 if (usetest && irl->o == IR_BAND && irl+1 == ir && !ra_used(irl)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2426 /* Combine comp(BAND(ref, r/imm), 0) into test mrm, r/imm. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2427 Reg right, left = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2428 RegSet allow = RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2429 if (!asm_isk32(as, irl->op2, &imm)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2430 left = ra_alloc1(as, irl->op2, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2431 rset_clear(allow, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2432 } else { /* Try to Fuse IRT_I8/IRT_U8 loads, too. See below. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2433 IRIns *irll = IR(irl->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2434 if (opisfusableload((IROp)irll->o) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2435 (irt_isi8(irll->t) \|\| irt_isu8(irll->t))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2436 IRType1 origt = irll->t; /* Temporarily flip types. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2437 irll->t.irt = (irll->t.irt & ~IRT_TYPE) \| IRT_INT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2438 as->curins--; /* Skip to BAND to avoid failing in noconflict(). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2439 right = asm_fuseload(as, irl->op1, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2440 as->curins++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2441 irll->t = origt;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2442 if (right != RID_MRM) goto test_nofuse;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2443 /* Fusion succeeded, emit test byte mrm, imm8. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2444 asm_guardcc(as, cc);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2445 emit_i8(as, (imm & 0xff));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2446 emit_mrm(as, XO_GROUP3b, XOg_TEST, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2447 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2448 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2449 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2450 as->curins--; /* Skip to BAND to avoid failing in noconflict(). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2451 right = asm_fuseloadm(as, irl->op1, allow, r64);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2452 as->curins++; /* Undo the above. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2453 test_nofuse:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2454 asm_guardcc(as, cc);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2455 if (ra_noreg(left)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2456 emit_i32(as, imm);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2457 emit_mrm(as, XO_GROUP3, r64 + XOg_TEST, right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2458 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2459 emit_mrm(as, XO_TEST, r64 + left, right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2460 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2461 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2462 Reg left;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2463 if (opisfusableload((IROp)irl->o) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2464 ((irt_isu8(irl->t) && checku8(imm)) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2465 ((irt_isi8(irl->t) \|\| irt_isi16(irl->t)) && checki8(imm)) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2466 (irt_isu16(irl->t) && checku16(imm) && checki8((int16_t)imm)))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2467 /* Only the IRT_INT case is fused by asm_fuseload.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2468 ** The IRT_I8/IRT_U8 loads and some IRT_I16/IRT_U16 loads
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2469 ** are handled here.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2470 ** Note that cmp word [mem], imm16 should not be generated,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2471 ** since it has a length-changing prefix. Compares of a word
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2472 ** against a sign-extended imm8 are ok, however.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2473 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2474 IRType1 origt = irl->t; /* Temporarily flip types. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2475 irl->t.irt = (irl->t.irt & ~IRT_TYPE) \| IRT_INT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2476 left = asm_fuseload(as, lref, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2477 irl->t = origt;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2478 if (left == RID_MRM) { /* Fusion succeeded? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2479 if (irt_isu8(irl->t) \|\| irt_isu16(irl->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2480 cc >>= 4; /* Need unsigned compare. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2481 asm_guardcc(as, cc);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2482 emit_i8(as, imm);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2483 emit_mrm(as, (irt_isi8(origt) \|\| irt_isu8(origt)) ?
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2484 XO_ARITHib : XO_ARITHiw8, r64 + XOg_CMP, RID_MRM);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2485 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2486 } /* Otherwise handle register case as usual. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2487 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2488 left = asm_fuseloadm(as, lref,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2489 irt_isu8(ir->t) ? RSET_GPR8 : RSET_GPR, r64);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2490 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2491 asm_guardcc(as, cc);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2492 if (usetest && left != RID_MRM) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2493 /* Use test r,r instead of cmp r,0. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2494 x86Op xo = XO_TEST;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2495 if (irt_isu8(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2496 lj_assertA(ir->o == IR_EQ \|\| ir->o == IR_NE, "bad usage");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2497 xo = XO_TESTb;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2498 if (!rset_test(RSET_RANGE(RID_EAX, RID_EBX+1), left)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2499 if (LJ_64) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2500 left \|= FORCE_REX;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2501 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2502 emit_i32(as, 0xff);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2503 emit_mrm(as, XO_GROUP3, XOg_TEST, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2504 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2505 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2506 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2507 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2508 emit_rr(as, xo, r64 + left, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2509 if (irl+1 == ir) /* Referencing previous ins? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2510 as->flagmcp = as->mcp; /* Set flag to drop test r,r if possible. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2511 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2512 emit_gmrmi(as, XG_ARITHi(XOg_CMP), r64 + left, imm);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2513 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2514 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2515 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2516 Reg left = ra_alloc1(as, lref, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2517 Reg right = asm_fuseloadm(as, rref, rset_exclude(RSET_GPR, left), r64);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2518 asm_guardcc(as, cc);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2519 emit_mrm(as, XO_CMP, r64 + left, right);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2520 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2521 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2522 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2523
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2524 #define asm_equal(as, ir) asm_comp(as, ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2525
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2526 #if LJ_32 && LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2527 /* 64 bit integer comparisons in 32 bit mode. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2528 static void asm_comp_int64(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2529 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2530 uint32_t cc = asm_compmap[(ir-1)->o];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2531 RegSet allow = RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2532 Reg lefthi = RID_NONE, leftlo = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2533 Reg righthi = RID_NONE, rightlo = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2534 MCLabel l_around;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2535 x86ModRM mrm;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2536
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2537 as->curins--; /* Skip loword ins. Avoids failing in noconflict(), too. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2538
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2539 /* Allocate/fuse hiword operands. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2540 if (irref_isk(ir->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2541 lefthi = asm_fuseload(as, ir->op1, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2542 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2543 lefthi = ra_alloc1(as, ir->op1, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2544 rset_clear(allow, lefthi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2545 righthi = asm_fuseload(as, ir->op2, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2546 if (righthi == RID_MRM) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2547 if (as->mrm.base != RID_NONE) rset_clear(allow, as->mrm.base);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2548 if (as->mrm.idx != RID_NONE) rset_clear(allow, as->mrm.idx);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2549 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2550 rset_clear(allow, righthi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2551 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2552 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2553 mrm = as->mrm; /* Save state for hiword instruction. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2554
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2555 /* Allocate/fuse loword operands. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2556 if (irref_isk((ir-1)->op2)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2557 leftlo = asm_fuseload(as, (ir-1)->op1, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2558 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2559 leftlo = ra_alloc1(as, (ir-1)->op1, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2560 rset_clear(allow, leftlo);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2561 rightlo = asm_fuseload(as, (ir-1)->op2, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2562 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2563
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2564 /* All register allocations must be performed _before_ this point. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2565 l_around = emit_label(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2566 as->invmcp = as->flagmcp = NULL; /* Cannot use these optimizations. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2567
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2568 /* Loword comparison and branch. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2569 asm_guardcc(as, cc >> 4); /* Always use unsigned compare for loword. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2570 if (ra_noreg(rightlo)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2571 int32_t imm = IR((ir-1)->op2)->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2572 if (imm == 0 && ((cc >> 4) & 0xa) != 0x2 && leftlo != RID_MRM)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2573 emit_rr(as, XO_TEST, leftlo, leftlo);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2574 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2575 emit_gmrmi(as, XG_ARITHi(XOg_CMP), leftlo, imm);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2576 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2577 emit_mrm(as, XO_CMP, leftlo, rightlo);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2578 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2579
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2580 /* Hiword comparison and branches. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2581 if ((cc & 15) != CC_NE)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2582 emit_sjcc(as, CC_NE, l_around); /* Hiword unequal: skip loword compare. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2583 if ((cc & 15) != CC_E)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2584 asm_guardcc(as, cc >> 8); /* Hiword compare without equality check. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2585 as->mrm = mrm; /* Restore state. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2586 if (ra_noreg(righthi)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2587 int32_t imm = IR(ir->op2)->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2588 if (imm == 0 && (cc & 0xa) != 0x2 && lefthi != RID_MRM)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2589 emit_rr(as, XO_TEST, lefthi, lefthi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2590 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2591 emit_gmrmi(as, XG_ARITHi(XOg_CMP), lefthi, imm);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2592 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2593 emit_mrm(as, XO_CMP, lefthi, righthi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2594 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2595 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2596 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2597
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2598 /* -- Split register ops -------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2599
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2600 /* Hiword op of a split 32/32 or 64/64 bit op. Previous op is the loword op. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2601 static void asm_hiop(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2602 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2603 /* HIOP is marked as a store because it needs its own DCE logic. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2604 int uselo = ra_used(ir-1), usehi = ra_used(ir); /* Loword/hiword used? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2605 if (LJ_UNLIKELY(!(as->flags & JIT_F_OPT_DCE))) uselo = usehi = 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2606 #if LJ_32 && LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2607 if ((ir-1)->o == IR_CONV) { /* Conversions to/from 64 bit. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2608 as->curins--; /* Always skip the CONV. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2609 if (usehi \|\| uselo)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2610 asm_conv64(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2611 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2612 } else if ((ir-1)->o <= IR_NE) { /* 64 bit integer comparisons. ORDER IR. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2613 asm_comp_int64(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2614 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2615 } else if ((ir-1)->o == IR_XSTORE) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2616 if ((ir-1)->r != RID_SINK)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2617 asm_fxstore(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2618 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2619 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2620 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2621 if (!usehi) return; /* Skip unused hiword op for all remaining ops. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2622 switch ((ir-1)->o) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2623 #if LJ_32 && LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2624 case IR_ADD:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2625 as->flagmcp = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2626 as->curins--;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2627 asm_intarith(as, ir, XOg_ADC);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2628 asm_intarith(as, ir-1, XOg_ADD);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2629 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2630 case IR_SUB:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2631 as->flagmcp = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2632 as->curins--;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2633 asm_intarith(as, ir, XOg_SBB);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2634 asm_intarith(as, ir-1, XOg_SUB);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2635 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2636 case IR_NEG: {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2637 Reg dest = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2638 emit_rr(as, XO_GROUP3, XOg_NEG, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2639 emit_i8(as, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2640 emit_rr(as, XO_ARITHi8, XOg_ADC, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2641 ra_left(as, dest, ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2642 as->curins--;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2643 asm_neg_not(as, ir-1, XOg_NEG);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2644 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2645 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2646 case IR_CNEWI:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2647 /* Nothing to do here. Handled by CNEWI itself. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2648 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2649 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2650 case IR_CALLN: case IR_CALLL: case IR_CALLS: case IR_CALLXS:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2651 if (!uselo)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2652 ra_allocref(as, ir->op1, RID2RSET(RID_RETLO)); /* Mark lo op as used. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2653 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2654 default: lj_assertA(0, "bad HIOP for op %d", (ir-1)->o); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2655 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2656 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2657
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2658 /* -- Profiling ----------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2659
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2660 static void asm_prof(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2661 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2662 UNUSED(ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2663 asm_guardcc(as, CC_NE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2664 emit_i8(as, HOOK_PROFILE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2665 emit_rma(as, XO_GROUP3b, XOg_TEST, &J2G(as->J)->hookmask);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2666 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2667
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2668 /* -- Stack handling ------------------------------------------------------ */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2669
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2670 /* Check Lua stack size for overflow. Use exit handler as fallback. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2671 static void asm_stack_check(ASMState *as, BCReg topslot,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2672 IRIns *irp, RegSet allow, ExitNo exitno)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2673 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2674 /* Try to get an unused temp. register, otherwise spill/restore eax. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2675 Reg pbase = irp ? irp->r : RID_BASE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2676 Reg r = allow ? rset_pickbot(allow) : RID_EAX;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2677 emit_jcc(as, CC_B, exitstub_addr(as->J, exitno));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2678 if (allow == RSET_EMPTY) /* Restore temp. register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2679 emit_rmro(as, XO_MOV, r\|REX_64, RID_ESP, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2680 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2681 ra_modified(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2682 emit_gri(as, XG_ARITHi(XOg_CMP), r\|REX_GC64, (int32_t)(8*topslot));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2683 if (ra_hasreg(pbase) && pbase != r)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2684 emit_rr(as, XO_ARITH(XOg_SUB), r\|REX_GC64, pbase);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2685 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2686 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2687 emit_rmro(as, XO_ARITH(XOg_SUB), r\|REX_64, RID_DISPATCH,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2688 (int32_t)dispofs(as, &J2G(as->J)->jit_base));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2689 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2690 emit_rmro(as, XO_ARITH(XOg_SUB), r, RID_NONE,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2691 ptr2addr(&J2G(as->J)->jit_base));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2692 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2693 emit_rmro(as, XO_MOV, r\|REX_GC64, r, offsetof(lua_State, maxstack));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2694 emit_getgl(as, r, cur_L);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2695 if (allow == RSET_EMPTY) /* Spill temp. register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2696 emit_rmro(as, XO_MOVto, r\|REX_64, RID_ESP, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2697 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2698
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2699 /* Restore Lua stack from on-trace state. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2700 static void asm_stack_restore(ASMState as, SnapShot snap)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2701 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2702 SnapEntry *map = &as->T->snapmap[snap->mapofs];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2703 #if !LJ_FR2 \|\| defined(LUA_USE_ASSERT)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2704 SnapEntry *flinks = &as->T->snapmap[snap_nextofs(as->T, snap)-1-LJ_FR2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2705 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2706 MSize n, nent = snap->nent;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2707 /* Store the value of all modified slots to the Lua stack. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2708 for (n = 0; n < nent; n++) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2709 SnapEntry sn = map[n];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2710 BCReg s = snap_slot(sn);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2711 int32_t ofs = 8*((int32_t)s-1-LJ_FR2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2712 IRRef ref = snap_ref(sn);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2713 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2714 if ((sn & SNAP_NORESTORE))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2715 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2716 if ((sn & SNAP_KEYINDEX)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2717 emit_movmroi(as, RID_BASE, ofs+4, LJ_KEYINDEX);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2718 if (irref_isk(ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2719 emit_movmroi(as, RID_BASE, ofs, ir->i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2720 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2721 Reg src = ra_alloc1(as, ref, rset_exclude(RSET_GPR, RID_BASE));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2722 emit_movtomro(as, src, RID_BASE, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2723 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2724 } else if (irt_isnum(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2725 Reg src = ra_alloc1(as, ref, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2726 emit_rmro(as, XO_MOVSDto, src, RID_BASE, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2727 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2728 lj_assertA(irt_ispri(ir->t) \|\| irt_isaddr(ir->t) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2729 (LJ_DUALNUM && irt_isinteger(ir->t)),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2730 "restore of IR type %d", irt_type(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2731 if (!irref_isk(ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2732 Reg src = ra_alloc1(as, ref, rset_exclude(RSET_GPR, RID_BASE));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2733 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2734 if (irt_is64(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2735 /* TODO: 64 bit store + 32 bit load-modify-store is suboptimal. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2736 emit_u32(as, irt_toitype(ir->t) << 15);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2737 emit_rmro(as, XO_ARITHi, XOg_OR, RID_BASE, ofs+4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2738 } else if (LJ_DUALNUM && irt_isinteger(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2739 emit_movmroi(as, RID_BASE, ofs+4, LJ_TISNUM << 15);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2740 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2741 emit_movmroi(as, RID_BASE, ofs+4, (irt_toitype(ir->t)<<15)\|0x7fff);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2742 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2743 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2744 emit_movtomro(as, REX_64IR(ir, src), RID_BASE, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2745 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2746 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2747 TValue k;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2748 lj_ir_kvalue(as->J->L, &k, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2749 if (tvisnil(&k)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2750 emit_i32(as, -1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2751 emit_rmro(as, XO_MOVmi, REX_64, RID_BASE, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2752 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2753 emit_movmroi(as, RID_BASE, ofs+4, k.u32.hi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2754 emit_movmroi(as, RID_BASE, ofs, k.u32.lo);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2755 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2756 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2757 } else if (!irt_ispri(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2758 emit_movmroi(as, RID_BASE, ofs, ir->i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2759 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2760 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2761 if ((sn & (SNAP_CONT\|SNAP_FRAME))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2762 #if !LJ_FR2
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2763 if (s != 0) /* Do not overwrite link to previous frame. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2764 emit_movmroi(as, RID_BASE, ofs+4, (int32_t)(*flinks--));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2765 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2766 #if !LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2767 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2768 if (!(LJ_64 && irt_islightud(ir->t)))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2769 emit_movmroi(as, RID_BASE, ofs+4, irt_toitype(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2770 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2771 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2772 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2773 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2774 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2775 lj_assertA(map + nent == flinks, "inconsistent frames in snapshot");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2776 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2777
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2778 /* -- GC handling --------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2779
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2780 /* Check GC threshold and do one or more GC steps. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2781 static void asm_gc_check(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2782 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2783 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_step_jit];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2784 IRRef args[2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2785 MCLabel l_end;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2786 Reg tmp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2787 ra_evictset(as, RSET_SCRATCH);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2788 l_end = emit_label(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2789 /* Exit trace if in GCSatomic or GCSfinalize. Avoids syncing GC objects. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2790 asm_guardcc(as, CC_NE); /* Assumes asm_snap_prep() already done. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2791 emit_rr(as, XO_TEST, RID_RET, RID_RET);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2792 args[0] = ASMREF_TMP1; /* global_State g /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2793 args[1] = ASMREF_TMP2; /* MSize steps */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2794 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2795 tmp = ra_releasetmp(as, ASMREF_TMP1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2796 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2797 emit_rmro(as, XO_LEA, tmp\|REX_64, RID_DISPATCH, GG_DISP2G);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2798 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2799 emit_loada(as, tmp, J2G(as->J));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2800 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2801 emit_loadi(as, ra_releasetmp(as, ASMREF_TMP2), as->gcsteps);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2802 /* Jump around GC step if GC total < GC threshold. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2803 emit_sjcc(as, CC_B, l_end);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2804 emit_opgl(as, XO_ARITH(XOg_CMP), tmp\|REX_GC64, gc.threshold);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2805 emit_getgl(as, tmp, gc.total);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2806 as->gcsteps = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2807 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2808 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2809
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2810 /* -- Loop handling ------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2811
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2812 /* Fixup the loop branch. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2813 static void asm_loop_fixup(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2814 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2815 MCode *p = as->mctop;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2816 MCode *target = as->mcp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2817 if (as->realign) { /* Realigned loops use short jumps. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2818 as->realign = NULL; /* Stop another retry. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2819 lj_assertA(((intptr_t)target & 15) == 0, "loop realign failed");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2820 if (as->loopinv) { /* Inverted loop branch? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2821 p -= 5;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2822 p[0] = XI_JMP;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2823 lj_assertA(target - p >= -128, "loop realign failed");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2824 p[-1] = (MCode)(target - p); /* Patch sjcc. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2825 if (as->loopinv == 2)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2826 p[-3] = (MCode)(target - p + 2); /* Patch opt. short jp. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2827 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2828 lj_assertA(target - p >= -128, "loop realign failed");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2829 p[-1] = (MCode)(int8_t)(target - p); /* Patch short jmp. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2830 p[-2] = XI_JMPs;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2831 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2832 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2833 MCode *newloop;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2834 p[-5] = XI_JMP;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2835 if (as->loopinv) { /* Inverted loop branch? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2836 /* asm_guardcc already inverted the jcc and patched the jmp. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2837 p -= 5;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2838 newloop = target+4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2839 (int32_t )(p-4) = (int32_t)(target - p); /* Patch jcc. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2840 if (as->loopinv == 2) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2841 (int32_t )(p-10) = (int32_t)(target - p + 6); /* Patch opt. jp. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2842 newloop = target+8;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2843 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2844 } else { /* Otherwise just patch jmp. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2845 (int32_t )(p-4) = (int32_t)(target - p);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2846 newloop = target+3;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2847 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2848 /* Realign small loops and shorten the loop branch. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2849 if (newloop >= p - 128) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2850 as->realign = newloop; /* Force a retry and remember alignment. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2851 as->curins = as->stopins; /* Abort asm_trace now. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2852 as->T->nins = as->orignins; /* Remove any added renames. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2853 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2854 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2855 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2856
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2857 /* Fixup the tail of the loop. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2858 static void asm_loop_tail_fixup(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2859 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2860 UNUSED(as); /* Nothing to do. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2861 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2862
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2863 /* -- Head of trace ------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2864
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2865 /* Coalesce BASE register for a root trace. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2866 static void asm_head_root_base(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2867 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2868 IRIns *ir = IR(REF_BASE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2869 Reg r = ir->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2870 if (ra_hasreg(r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2871 ra_free(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2872 if (rset_test(as->modset, r) \|\| irt_ismarked(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2873 ir->r = RID_INIT; /* No inheritance for modified BASE register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2874 if (r != RID_BASE)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2875 emit_rr(as, XO_MOV, r\|REX_GC64, RID_BASE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2876 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2877 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2878
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2879 /* Coalesce or reload BASE register for a side trace. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2880 static Reg asm_head_side_base(ASMState as, IRIns irp)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2881 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2882 IRIns *ir = IR(REF_BASE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2883 Reg r = ir->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2884 if (ra_hasreg(r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2885 ra_free(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2886 if (rset_test(as->modset, r) \|\| irt_ismarked(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2887 ir->r = RID_INIT; /* No inheritance for modified BASE register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2888 if (irp->r == r) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2889 return r; /* Same BASE register already coalesced. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2890 } else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2891 /* Move from coalesced parent reg. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2892 emit_rr(as, XO_MOV, r\|REX_GC64, irp->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2893 return irp->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2894 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2895 emit_getgl(as, r, jit_base); /* Otherwise reload BASE. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2896 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2897 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2898 return RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2899 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2900
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2901 /* -- Tail of trace ------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2902
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2903 /* Fixup the tail code. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2904 static void asm_tail_fixup(ASMState *as, TraceNo lnk)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2905 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2906 /* Note: don't use as->mcp swap + emit_: emit_op overwrites more bytes. /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2907 MCode *p = as->mctop;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2908 MCode target, q;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2909 int32_t spadj = as->T->spadjust;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2910 if (spadj == 0) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2911 p -= LJ_64 ? 7 : 6;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2912 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2913 MCode *p1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2914 /* Patch stack adjustment. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2915 if (checki8(spadj)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2916 p -= 3;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2917 p1 = p-6;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2918 *p1 = (MCode)spadj;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2919 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2920 p1 = p-9;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2921 (int32_t )p1 = spadj;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2922 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2923 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2924 p1[-3] = 0x48;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2925 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2926 p1[-2] = (MCode)(checki8(spadj) ? XI_ARITHi8 : XI_ARITHi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2927 p1[-1] = MODRM(XM_REG, XOg_ADD, RID_ESP);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2928 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2929 /* Patch exit branch. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2930 target = lnk ? traceref(as->J, lnk)->mcode : (MCode *)lj_vm_exit_interp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2931 (int32_t )(p-4) = jmprel(as->J, p, target);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2932 p[-5] = XI_JMP;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2933 /* Drop unused mcode tail. Fill with NOPs to make the prefetcher happy. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2934 for (q = as->mctop-1; q >= p; q--)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2935 *q = XI_NOP;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2936 as->mctop = p;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2937 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2938
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2939 /* Prepare tail of code. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2940 static void asm_tail_prep(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2941 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2942 MCode *p = as->mctop;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2943 /* Realign and leave room for backwards loop branch or exit branch. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2944 if (as->realign) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2945 int i = ((int)(intptr_t)as->realign) & 15;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2946 /* Fill unused mcode tail with NOPs to make the prefetcher happy. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2947 while (i-- > 0)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2948 *--p = XI_NOP;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2949 as->mctop = p;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2950 p -= (as->loopinv ? 5 : 2); /* Space for short/near jmp. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2951 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2952 p -= 5; /* Space for exit branch (near jmp). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2953 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2954 if (as->loopref) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2955 as->invmcp = as->mcp = p;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2956 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2957 /* Leave room for ESP adjustment: add esp, imm or lea esp, [esp+imm] */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2958 as->mcp = p - (LJ_64 ? 7 : 6);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2959 as->invmcp = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2960 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2961 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2962
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2963 /* -- Trace setup --------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2964
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2965 /* Ensure there are enough stack slots for call arguments. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2966 static Reg asm_setup_call_slots(ASMState as, IRIns ir, const CCallInfo *ci)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2967 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2968 IRRef args[CCI_NARGS_MAX*2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2969 int nslots;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2970 asm_collectargs(as, ir, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2971 nslots = asm_count_call_slots(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2972 if (nslots > as->evenspill) /* Leave room for args in stack slots. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2973 as->evenspill = nslots;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2974 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2975 return irt_isfp(ir->t) ? REGSP_HINT(RID_FPRET) : REGSP_HINT(RID_RET);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2976 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2977 return irt_isfp(ir->t) ? REGSP_INIT : REGSP_HINT(RID_RET);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2978 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2979 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2980
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2981 /* Target-specific setup. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2982 static void asm_setup_target(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2983 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2984 asm_exitstub_setup(as, as->T->nsnap);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2985 as->mrm.base = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2986 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2987
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2988 /* -- Trace patching ------------------------------------------------------ */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2989
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2990 static const uint8_t map_op1[256] = {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2991 0x92,0x92,0x92,0x92,0x52,0x45,0x51,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x51,0x20,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2992 0x92,0x92,0x92,0x92,0x52,0x45,0x51,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x51,0x51,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2993 0x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2994 0x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2995 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2996 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2997 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2998 0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2999 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3000 0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3001 0x51,0x51,0x92,0x92,0x10,0x10,0x12,0x11,0x45,0x86,0x52,0x93,0x51,0x51,0x51,0x51,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3002 0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3003 0x93,0x86,0x93,0x93,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3004 0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x47,0x51,0x51,0x51,0x51,0x51,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3005 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3006 0x59,0x59,0x59,0x59,0x51,0x51,0x51,0x51,0x52,0x45,0x51,0x51,0x51,0x51,0x51,0x51,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3007 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3008 0x55,0x55,0x55,0x55,0x51,0x51,0x51,0x51,0x52,0x45,0x51,0x51,0x51,0x51,0x51,0x51,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3009 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3010 0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x05,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3011 0x93,0x93,0x53,0x51,0x70,0x71,0x93,0x86,0x54,0x51,0x53,0x51,0x51,0x52,0x51,0x51,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3012 0x92,0x92,0x92,0x92,0x52,0x52,0x51,0x51,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3013 0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x45,0x45,0x47,0x52,0x51,0x51,0x51,0x51,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3014 0x10,0x51,0x10,0x10,0x51,0x51,0x63,0x66,0x51,0x51,0x51,0x51,0x51,0x51,0x92,0x92
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3015 };
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3016
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3017 static const uint8_t map_op2[256] = {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3018 0x93,0x93,0x93,0x93,0x52,0x52,0x52,0x52,0x52,0x52,0x51,0x52,0x51,0x93,0x52,0x94,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3019 0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3020 0x53,0x53,0x53,0x53,0x53,0x53,0x53,0x53,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3021 0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x34,0x51,0x35,0x51,0x51,0x51,0x51,0x51,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3022 0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3023 0x53,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3024 0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3025 0x94,0x54,0x54,0x54,0x93,0x93,0x93,0x52,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3026 0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,0x46,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3027 0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3028 0x52,0x52,0x52,0x93,0x94,0x93,0x51,0x51,0x52,0x52,0x52,0x93,0x94,0x93,0x93,0x93,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3029 0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x94,0x93,0x93,0x93,0x93,0x93,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3030 0x93,0x93,0x94,0x93,0x94,0x94,0x94,0x93,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3031 0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3032 0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3033 0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x52
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3034 };
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3035
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3036 static uint32_t asm_x86_inslen(const uint8_t* p)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3037 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3038 uint32_t result = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3039 uint32_t prefixes = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3040 uint32_t x = map_op1[*p];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3041 for (;;) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3042 switch (x >> 4) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3043 case 0: return result + x + (prefixes & 4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3044 case 1: prefixes \|= x; x = map_op1[*++p]; result++; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3045 case 2: x = map_op2[*++p]; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3046 case 3: p++; goto mrm;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3047 case 4: result -= (prefixes & 2); /* fallthrough */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3048 case 5: return result + (x & 15);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3049 case 6: /* Group 3. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3050 if (p[1] & 0x38) x = 2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3051 else if ((prefixes & 2) && (x == 0x66)) x = 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3052 goto mrm;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3053 case 7: /* VEX c4/c5. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3054 if (LJ_32 && p[1] < 0xc0) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3055 x = 2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3056 goto mrm;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3057 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3058 if (x == 0x70) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3059 x = *++p & 0x1f;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3060 result++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3061 if (x >= 2) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3062 p += 2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3063 result += 2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3064 goto mrm;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3065 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3066 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3067 p++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3068 result++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3069 x = map_op2[*++p];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3070 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3071 case 8: result -= (prefixes & 2); /* fallthrough */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3072 case 9: mrm: /* ModR/M and possibly SIB. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3073 result += (x & 15);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3074 x = *++p;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3075 switch (x >> 6) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3076 case 0: if ((x & 7) == 5) return result + 4; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3077 case 1: result++; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3078 case 2: result += 4; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3079 case 3: return result;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3080 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3081 if ((x & 7) == 4) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3082 result++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3083 if (x < 0x40 && (p[1] & 7) == 5) result += 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3084 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3085 return result;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3086 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3087 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3088 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3089
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3090 /* Patch exit jumps of existing machine code to a new target. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3091 void lj_asm_patchexit(jit_State J, GCtrace T, ExitNo exitno, MCode *target)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3092 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3093 MCode *p = T->mcode;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3094 MCode *mcarea = lj_mcode_patch(J, p, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3095 MSize len = T->szmcode;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3096 MCode *px = exitstub_addr(J, exitno) - 6;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3097 MCode *pe = p+len-6;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3098 MCode *pgc = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3099 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3100 uint32_t statei = (uint32_t)(GG_OFS(g.vmstate) - GG_OFS(dispatch));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3101 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3102 uint32_t statei = u32ptr(&J2G(J)->vmstate);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3103 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3104 if (len > 5 && p[len-5] == XI_JMP && p+len-6 + (int32_t )(p+len-4) == px)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3105 (int32_t )(p+len-4) = jmprel(J, p+len, target);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3106 /* Do not patch parent exit for a stack check. Skip beyond vmstate update. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3107 for (; p < pe; p += asm_x86_inslen(p)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3108 intptr_t ofs = LJ_GC64 ? (p[0] & 0xf0) == 0x40 : LJ_64;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3109 if ((uint32_t )(p+2+ofs) == statei && p[ofs+LJ_GC64-LJ_64] == XI_MOVmi)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3110 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3111 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3112 lj_assertJ(p < pe, "instruction length decoder failed");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3113 for (; p < pe; p += asm_x86_inslen(p)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3114 if (((uint16_t )p & 0xf0ff) == 0x800f && p + (int32_t )(p+2) == px &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3115 p != pgc) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3116 (int32_t )(p+2) = jmprel(J, p+6, target);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3117 } else if (*p == XI_CALL &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3118 (void )(p+5+(int32_t )(p+1)) == (void )lj_gc_step_jit) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3119 pgc = p+7; /* Do not patch GC check exit. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3120 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3121 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3122 lj_mcode_sync(T->mcode, T->mcode + T->szmcode);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3123 lj_mcode_patch(J, mcarea, 1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3124 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3125

Mercurial

annotate third_party/luajit/src/lj_asm_x86.h @ 279:b3b547563ec7