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annotate third_party/luajit/src/lj_target_mips.h @ 200:90dfcef375fb

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Added my own s3 bucket uploader url to mrjunejune.
author MrJuneJune <me@mrjunejune.com>
date Sat, 14 Feb 2026 16:32:24 -0800
parents 94705b5986b3
children
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178
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1 /*
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2 ** Definitions for MIPS CPUs.
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3 ** Copyright (C) 2005-2023 Mike Pall. See Copyright Notice in luajit.h
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4 */
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5
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6 #ifndef _LJ_TARGET_MIPS_H
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7 #define _LJ_TARGET_MIPS_H
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8
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9 /* -- Registers IDs ------------------------------------------------------- */
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10
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11 #define GPRDEF(_) \
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12 _(R0) _(R1) _(R2) _(R3) _(R4) _(R5) _(R6) _(R7) \
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13 _(R8) _(R9) _(R10) _(R11) _(R12) _(R13) _(R14) _(R15) \
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14 _(R16) _(R17) _(R18) _(R19) _(R20) _(R21) _(R22) _(R23) \
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15 _(R24) _(R25) _(SYS1) _(SYS2) _(R28) _(SP) _(R30) _(RA)
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16 #if LJ_SOFTFP
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17 #define FPRDEF(_)
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18 #else
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19 #define FPRDEF(_) \
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20 _(F0) _(F1) _(F2) _(F3) _(F4) _(F5) _(F6) _(F7) \
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21 _(F8) _(F9) _(F10) _(F11) _(F12) _(F13) _(F14) _(F15) \
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22 _(F16) _(F17) _(F18) _(F19) _(F20) _(F21) _(F22) _(F23) \
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23 _(F24) _(F25) _(F26) _(F27) _(F28) _(F29) _(F30) _(F31)
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24 #endif
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25 #define VRIDDEF(_)
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26
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27 #define RIDENUM(name) RID_##name,
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28
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29 enum {
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30 GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */
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31 FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */
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32 RID_MAX,
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33 RID_ZERO = RID_R0,
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34 RID_TMP = RID_RA,
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35 RID_GP = RID_R28,
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36
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37 /* Calling conventions. */
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38 RID_RET = RID_R2,
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39 #if LJ_LE
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40 RID_RETHI = RID_R3,
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41 RID_RETLO = RID_R2,
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42 #else
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43 RID_RETHI = RID_R2,
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44 RID_RETLO = RID_R3,
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45 #endif
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46 #if LJ_SOFTFP
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47 RID_FPRET = RID_R2,
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48 #else
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49 RID_FPRET = RID_F0,
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50 #endif
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51 RID_CFUNCADDR = RID_R25,
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52
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53 /* These definitions must match with the *.dasc file(s): */
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54 RID_BASE = RID_R16, /* Interpreter BASE. */
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55 RID_LPC = RID_R18, /* Interpreter PC. */
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56 RID_DISPATCH = RID_R19, /* Interpreter DISPATCH table. */
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57 RID_LREG = RID_R20, /* Interpreter L. */
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58 RID_JGL = RID_R30, /* On-trace: global_State + 32768. */
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59
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60 /* Register ranges [min, max) and number of registers. */
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61 RID_MIN_GPR = RID_R0,
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62 RID_MAX_GPR = RID_RA+1,
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63 RID_MIN_FPR = RID_MAX_GPR,
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64 #if LJ_SOFTFP
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65 RID_MAX_FPR = RID_MIN_FPR,
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66 #else
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67 RID_MAX_FPR = RID_F31+1,
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68 #endif
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69 RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR,
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70 RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR /* Only even regs are used. */
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71 };
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72
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73 #define RID_NUM_KREF RID_NUM_GPR
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74 #define RID_MIN_KREF RID_R0
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75
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76 /* -- Register sets ------------------------------------------------------- */
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77
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78 /* Make use of all registers, except ZERO, TMP, SP, SYS1, SYS2, JGL and GP. */
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79 #define RSET_FIXED \
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80 (RID2RSET(RID_ZERO)|RID2RSET(RID_TMP)|RID2RSET(RID_SP)|\
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81 RID2RSET(RID_SYS1)|RID2RSET(RID_SYS2)|RID2RSET(RID_JGL)|RID2RSET(RID_GP))
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82 #define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) - RSET_FIXED)
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83 #if LJ_SOFTFP
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84 #define RSET_FPR 0
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85 #else
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86 #if LJ_32
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87 #define RSET_FPR \
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88 (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\
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89 RID2RSET(RID_F8)|RID2RSET(RID_F10)|RID2RSET(RID_F12)|RID2RSET(RID_F14)|\
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90 RID2RSET(RID_F16)|RID2RSET(RID_F18)|RID2RSET(RID_F20)|RID2RSET(RID_F22)|\
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91 RID2RSET(RID_F24)|RID2RSET(RID_F26)|RID2RSET(RID_F28)|RID2RSET(RID_F30))
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92 #else
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93 #define RSET_FPR RSET_RANGE(RID_MIN_FPR, RID_MAX_FPR)
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94 #endif
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95 #endif
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96 #define RSET_ALL (RSET_GPR|RSET_FPR)
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97 #define RSET_INIT RSET_ALL
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98
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99 #define RSET_SCRATCH_GPR \
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100 (RSET_RANGE(RID_R1, RID_R15+1)|\
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101 RID2RSET(RID_R24)|RID2RSET(RID_R25))
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102 #if LJ_SOFTFP
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103 #define RSET_SCRATCH_FPR 0
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104 #else
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105 #if LJ_32
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106 #define RSET_SCRATCH_FPR \
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107 (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\
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108 RID2RSET(RID_F8)|RID2RSET(RID_F10)|RID2RSET(RID_F12)|RID2RSET(RID_F14)|\
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109 RID2RSET(RID_F16)|RID2RSET(RID_F18))
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110 #else
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111 #define RSET_SCRATCH_FPR RSET_RANGE(RID_F0, RID_F24)
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112 #endif
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113 #endif
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114 #define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR)
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115 #define REGARG_FIRSTGPR RID_R4
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116 #if LJ_32
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117 #define REGARG_LASTGPR RID_R7
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118 #define REGARG_NUMGPR 4
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119 #else
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120 #define REGARG_LASTGPR RID_R11
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121 #define REGARG_NUMGPR 8
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122 #endif
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123 #if LJ_ABI_SOFTFP
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124 #define REGARG_FIRSTFPR 0
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125 #define REGARG_LASTFPR 0
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126 #define REGARG_NUMFPR 0
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127 #else
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128 #define REGARG_FIRSTFPR RID_F12
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129 #if LJ_32
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130 #define REGARG_LASTFPR RID_F14
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131 #define REGARG_NUMFPR 2
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132 #else
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133 #define REGARG_LASTFPR RID_F19
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134 #define REGARG_NUMFPR 8
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135 #endif
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136 #endif
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137
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138 /* -- Spill slots --------------------------------------------------------- */
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139
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140 /* Spill slots are 32 bit wide. An even/odd pair is used for FPRs.
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141 **
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142 ** SPS_FIXED: Available fixed spill slots in interpreter frame.
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143 ** This definition must match with the *.dasc file(s).
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144 **
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145 ** SPS_FIRST: First spill slot for general use.
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146 */
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147 #if LJ_32
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148 #define SPS_FIXED 5
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149 #else
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150 #define SPS_FIXED 4
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151 #endif
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152 #define SPS_FIRST 4
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153
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154 #define SPOFS_TMP 0
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155
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156 #define sps_scale(slot) (4 * (int32_t)(slot))
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157 #define sps_align(slot) (((slot) - SPS_FIXED + 1) & ~1)
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158
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159 /* -- Exit state ---------------------------------------------------------- */
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160
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161 /* This definition must match with the *.dasc file(s). */
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162 typedef struct {
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163 #if !LJ_SOFTFP
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164 lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */
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165 #endif
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166 intptr_t gpr[RID_NUM_GPR]; /* General-purpose registers. */
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167 int32_t spill[256]; /* Spill slots. */
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168 } ExitState;
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169
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170 /* Highest exit + 1 indicates stack check. */
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171 #define EXITSTATE_CHECKEXIT 1
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172
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173 /* Return the address of a per-trace exit stub. */
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174 static LJ_AINLINE uint32_t *exitstub_trace_addr_(uint32_t *p)
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175 {
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176 while (*p == 0x00000000) p++; /* Skip MIPSI_NOP. */
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177 return p;
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178 }
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179 /* Avoid dependence on lj_jit.h if only including lj_target.h. */
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180 #define exitstub_trace_addr(T, exitno) \
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181 exitstub_trace_addr_((MCode *)((char *)(T)->mcode + (T)->szmcode))
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182
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diff changeset
183 /* -- Instructions -------------------------------------------------------- */
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184
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185 /* Instruction fields. */
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186 #define MIPSF_S(r) ((r) << 21)
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187 #define MIPSF_T(r) ((r) << 16)
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188 #define MIPSF_D(r) ((r) << 11)
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189 #define MIPSF_R(r) ((r) << 21)
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190 #define MIPSF_H(r) ((r) << 16)
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191 #define MIPSF_G(r) ((r) << 11)
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192 #define MIPSF_F(r) ((r) << 6)
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193 #define MIPSF_A(n) ((n) << 6)
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194 #define MIPSF_M(n) ((n) << 11)
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195 #define MIPSF_L(n) ((n) << 6)
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196
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197 typedef enum MIPSIns {
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198 MIPSI_D = 0x38,
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199 MIPSI_DV = 0x10,
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200 MIPSI_D32 = 0x3c,
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201 /* Integer instructions. */
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202 MIPSI_MOVE = 0x00000025,
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diff changeset
203 MIPSI_NOP = 0x00000000,
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diff changeset
204
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205 MIPSI_LI = 0x24000000,
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diff changeset
206 MIPSI_LU = 0x34000000,
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diff changeset
207 MIPSI_LUI = 0x3c000000,
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208
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209 MIPSI_AND = 0x00000024,
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diff changeset
210 MIPSI_ANDI = 0x30000000,
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211 MIPSI_OR = 0x00000025,
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diff changeset
212 MIPSI_ORI = 0x34000000,
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213 MIPSI_XOR = 0x00000026,
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214 MIPSI_XORI = 0x38000000,
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diff changeset
215 MIPSI_NOR = 0x00000027,
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diff changeset
216
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217 MIPSI_SLT = 0x0000002a,
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218 MIPSI_SLTU = 0x0000002b,
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219 MIPSI_SLTI = 0x28000000,
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220 MIPSI_SLTIU = 0x2c000000,
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diff changeset
221
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diff changeset
222 MIPSI_ADDU = 0x00000021,
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223 MIPSI_ADDIU = 0x24000000,
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diff changeset
224 MIPSI_SUB = 0x00000022,
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diff changeset
225 MIPSI_SUBU = 0x00000023,
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226
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diff changeset
227 #if !LJ_TARGET_MIPSR6
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228 MIPSI_MUL = 0x70000002,
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229 MIPSI_DIV = 0x0000001a,
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230 MIPSI_DIVU = 0x0000001b,
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diff changeset
231
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diff changeset
232 MIPSI_MOVZ = 0x0000000a,
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diff changeset
233 MIPSI_MOVN = 0x0000000b,
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diff changeset
234 MIPSI_MFHI = 0x00000010,
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diff changeset
235 MIPSI_MFLO = 0x00000012,
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diff changeset
236 MIPSI_MULT = 0x00000018,
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diff changeset
237 #else
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diff changeset
238 MIPSI_MUL = 0x00000098,
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diff changeset
239 MIPSI_MUH = 0x000000d8,
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diff changeset
240 MIPSI_DIV = 0x0000009a,
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parents:
diff changeset
241 MIPSI_DIVU = 0x0000009b,
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diff changeset
242
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diff changeset
243 MIPSI_SELEQZ = 0x00000035,
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diff changeset
244 MIPSI_SELNEZ = 0x00000037,
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parents:
diff changeset
245 #endif
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diff changeset
246
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diff changeset
247 MIPSI_SLL = 0x00000000,
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diff changeset
248 MIPSI_SRL = 0x00000002,
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diff changeset
249 MIPSI_SRA = 0x00000003,
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diff changeset
250 MIPSI_ROTR = 0x00200002, /* MIPSXXR2 */
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MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
251 MIPSI_DROTR = 0x0020003a,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
252 MIPSI_DROTR32 = 0x0020003e,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
253 MIPSI_SLLV = 0x00000004,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
254 MIPSI_SRLV = 0x00000006,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
255 MIPSI_SRAV = 0x00000007,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
256 MIPSI_ROTRV = 0x00000046, /* MIPSXXR2 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
257 MIPSI_DROTRV = 0x00000056,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
258
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
259 MIPSI_INS = 0x7c000004, /* MIPSXXR2 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
260
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
261 MIPSI_SEB = 0x7c000420, /* MIPSXXR2 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
262 MIPSI_SEH = 0x7c000620, /* MIPSXXR2 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
263 MIPSI_WSBH = 0x7c0000a0, /* MIPSXXR2 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
264 MIPSI_DSBH = 0x7c0000a4,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
265
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
266 MIPSI_B = 0x10000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
267 MIPSI_J = 0x08000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
268 MIPSI_JAL = 0x0c000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
269 #if !LJ_TARGET_MIPSR6
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
270 MIPSI_JALX = 0x74000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
271 MIPSI_JR = 0x00000008,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
272 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
273 MIPSI_JR = 0x00000009,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
274 MIPSI_BALC = 0xe8000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
275 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
276 MIPSI_JALR = 0x0000f809,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
277
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
278 MIPSI_BEQ = 0x10000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
279 MIPSI_BNE = 0x14000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
280 MIPSI_BLEZ = 0x18000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
281 MIPSI_BGTZ = 0x1c000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
282 MIPSI_BLTZ = 0x04000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
283 MIPSI_BGEZ = 0x04010000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
284
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
285 /* Load/store instructions. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
286 MIPSI_LW = 0x8c000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
287 MIPSI_LD = 0xdc000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
288 MIPSI_SW = 0xac000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
289 MIPSI_SD = 0xfc000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
290 MIPSI_LB = 0x80000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
291 MIPSI_SB = 0xa0000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
292 MIPSI_LH = 0x84000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
293 MIPSI_SH = 0xa4000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
294 MIPSI_LBU = 0x90000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
295 MIPSI_LHU = 0x94000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
296 MIPSI_LWC1 = 0xc4000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
297 MIPSI_SWC1 = 0xe4000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
298 MIPSI_LDC1 = 0xd4000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
299 MIPSI_SDC1 = 0xf4000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
300
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
301 /* MIPS64 instructions. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
302 MIPSI_DADD = 0x0000002c,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
303 MIPSI_DADDU = 0x0000002d,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
304 MIPSI_DADDIU = 0x64000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
305 MIPSI_DSUB = 0x0000002e,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
306 MIPSI_DSUBU = 0x0000002f,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
307 #if !LJ_TARGET_MIPSR6
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
308 MIPSI_DDIV = 0x0000001e,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
309 MIPSI_DDIVU = 0x0000001f,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
310 MIPSI_DMULT = 0x0000001c,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
311 MIPSI_DMULTU = 0x0000001d,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
312 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
313 MIPSI_DDIV = 0x0000009e,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
314 MIPSI_DMOD = 0x000000de,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
315 MIPSI_DDIVU = 0x0000009f,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
316 MIPSI_DMODU = 0x000000df,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
317 MIPSI_DMUL = 0x0000009c,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
318 MIPSI_DMUH = 0x000000dc,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
319 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
320
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
321 MIPSI_DSLL = 0x00000038,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
322 MIPSI_DSRL = 0x0000003a,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
323 MIPSI_DSLLV = 0x00000014,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
324 MIPSI_DSRLV = 0x00000016,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
325 MIPSI_DSRA = 0x0000003b,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
326 MIPSI_DSRAV = 0x00000017,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
327 MIPSI_DSRA32 = 0x0000003f,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
328 MIPSI_DSLL32 = 0x0000003c,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
329 MIPSI_DSRL32 = 0x0000003e,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
330 MIPSI_DSHD = 0x7c000164,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
331
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
332 MIPSI_AADDU = LJ_32 ? MIPSI_ADDU : MIPSI_DADDU,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
333 MIPSI_AADDIU = LJ_32 ? MIPSI_ADDIU : MIPSI_DADDIU,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
334 MIPSI_ASUBU = LJ_32 ? MIPSI_SUBU : MIPSI_DSUBU,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
335 MIPSI_AL = LJ_32 ? MIPSI_LW : MIPSI_LD,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
336 MIPSI_AS = LJ_32 ? MIPSI_SW : MIPSI_SD,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
337 #if LJ_TARGET_MIPSR6
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
338 MIPSI_LSA = 0x00000005,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
339 MIPSI_DLSA = 0x00000015,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
340 MIPSI_ALSA = LJ_32 ? MIPSI_LSA : MIPSI_DLSA,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
341 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
342
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
343 /* Extract/insert instructions. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
344 MIPSI_DEXTM = 0x7c000001,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
345 MIPSI_DEXTU = 0x7c000002,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
346 MIPSI_DEXT = 0x7c000003,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
347 MIPSI_DINSM = 0x7c000005,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
348 MIPSI_DINSU = 0x7c000006,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
349 MIPSI_DINS = 0x7c000007,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
350
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
351 MIPSI_FLOOR_D = 0x4620000b,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
352
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
353 /* FP instructions. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
354 MIPSI_MOV_S = 0x46000006,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
355 MIPSI_MOV_D = 0x46200006,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
356 #if !LJ_TARGET_MIPSR6
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
357 MIPSI_MOVT_D = 0x46210011,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
358 MIPSI_MOVF_D = 0x46200011,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
359 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
360 MIPSI_MIN_D = 0x4620001C,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
361 MIPSI_MAX_D = 0x4620001E,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
362 MIPSI_SEL_D = 0x46200010,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
363 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
364
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
365 MIPSI_ABS_D = 0x46200005,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
366 MIPSI_NEG_D = 0x46200007,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
367
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
368 MIPSI_ADD_D = 0x46200000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
369 MIPSI_SUB_D = 0x46200001,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
370 MIPSI_MUL_D = 0x46200002,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
371 MIPSI_DIV_D = 0x46200003,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
372 MIPSI_SQRT_D = 0x46200004,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
373
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
374 MIPSI_ADD_S = 0x46000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
375 MIPSI_SUB_S = 0x46000001,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
376
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
377 MIPSI_CVT_D_S = 0x46000021,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
378 MIPSI_CVT_W_S = 0x46000024,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
379 MIPSI_CVT_S_D = 0x46200020,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
380 MIPSI_CVT_W_D = 0x46200024,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
381 MIPSI_CVT_S_W = 0x46800020,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
382 MIPSI_CVT_D_W = 0x46800021,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
383 MIPSI_CVT_S_L = 0x46a00020,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
384 MIPSI_CVT_D_L = 0x46a00021,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
385
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
386 MIPSI_TRUNC_W_S = 0x4600000d,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
387 MIPSI_TRUNC_W_D = 0x4620000d,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
388 MIPSI_TRUNC_L_S = 0x46000009,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
389 MIPSI_TRUNC_L_D = 0x46200009,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
390 MIPSI_FLOOR_W_S = 0x4600000f,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
391 MIPSI_FLOOR_W_D = 0x4620000f,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
392
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
393 MIPSI_MFC1 = 0x44000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
394 MIPSI_MTC1 = 0x44800000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
395 MIPSI_DMTC1 = 0x44a00000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
396 MIPSI_DMFC1 = 0x44200000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
397
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
398 #if !LJ_TARGET_MIPSR6
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
399 MIPSI_BC1F = 0x45000000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
400 MIPSI_BC1T = 0x45010000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
401 MIPSI_C_EQ_D = 0x46200032,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
402 MIPSI_C_OLT_S = 0x46000034,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
403 MIPSI_C_OLT_D = 0x46200034,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
404 MIPSI_C_ULT_D = 0x46200035,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
405 MIPSI_C_OLE_D = 0x46200036,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
406 MIPSI_C_ULE_D = 0x46200037,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
407 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
408 MIPSI_BC1EQZ = 0x45200000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
409 MIPSI_BC1NEZ = 0x45a00000,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
410 MIPSI_CMP_EQ_D = 0x46a00002,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
411 MIPSI_CMP_LT_S = 0x46800004,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
412 MIPSI_CMP_LT_D = 0x46a00004,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
413 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
414
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
415 } MIPSIns;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
416
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing.
MrJuneJune <me@mrjunejune.com>
parents:
diff changeset
417 #endif