/home/mrjunejune/zenbu: third_party/luajit/src/lj

annotate third_party/luajit/src/lj_asm.c @ 214:4c725fde6999

[MrJuneJune] Fixed linkedin path and images modules.

author	MrJuneJune <me@mrjunejune.com>
date	Sun, 15 Feb 2026 22:21:27 -0800
parents	94705b5986b3
children

rev	line source
178 94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1 /*
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2 ** IR assembler (SSA IR -> machine code).
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	3 ** Copyright (C) 2005-2023 Mike Pall. See Copyright Notice in luajit.h
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	4 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	5
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	6 #define lj_asm_c
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	7 #define LUA_CORE
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	8
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	9 #include "lj_obj.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	10
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	11 #if LJ_HASJIT
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	12
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	13 #include "lj_gc.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	14 #include "lj_buf.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	15 #include "lj_str.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	16 #include "lj_tab.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	17 #include "lj_frame.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	18 #if LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	19 #include "lj_ctype.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	20 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	21 #include "lj_ir.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	22 #include "lj_jit.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	23 #include "lj_ircall.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	24 #include "lj_iropt.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	25 #include "lj_mcode.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	26 #include "lj_trace.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	27 #include "lj_snap.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	28 #include "lj_asm.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	29 #include "lj_dispatch.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	30 #include "lj_vm.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	31 #include "lj_target.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	32
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	33 #ifdef LUA_USE_ASSERT
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	34 #include <stdio.h>
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	35 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	36
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	37 /* -- Assembler state and common macros ----------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	38
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	39 /* Assembler state. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	40 typedef struct ASMState {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	41 RegCost cost[RID_MAX]; /* Reference and blended allocation cost for regs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	42
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	43 MCode mcp; / Current MCode pointer (grows down). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	44 MCode mclim; / Lower limit for MCode memory + red zone. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	45 #ifdef LUA_USE_ASSERT
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	46 MCode mcp_prev; / Red zone overflow check. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	47 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	48
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	49 IRIns ir; / Copy of pointer to IR instructions/constants. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	50 jit_State J; / JIT compiler state. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	51
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	52 #if LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	53 x86ModRM mrm; /* Fused x86 address operand. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	54 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	55
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	56 RegSet freeset; /* Set of free registers. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	57 RegSet modset; /* Set of registers modified inside the loop. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	58 RegSet weakset; /* Set of weakly referenced registers. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	59 RegSet phiset; /* Set of PHI registers. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	60
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	61 uint32_t flags; /* Copy of JIT compiler flags. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	62 int loopinv; /* Loop branch inversion (0:no, 1:yes, 2:yes+CC_P). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	63
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	64 int32_t evenspill; /* Next even spill slot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	65 int32_t oddspill; /* Next odd spill slot (or 0). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	66
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	67 IRRef curins; /* Reference of current instruction. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	68 IRRef stopins; /* Stop assembly before hitting this instruction. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	69 IRRef orignins; /* Original T->nins. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	70
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	71 IRRef snapref; /* Current snapshot is active after this reference. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	72 IRRef snaprename; /* Rename highwater mark for snapshot check. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	73 SnapNo snapno; /* Current snapshot number. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	74 SnapNo loopsnapno; /* Loop snapshot number. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	75 int snapalloc; /* Current snapshot needs allocation. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	76 BloomFilter snapfilt1, snapfilt2; /* Filled with snapshot refs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	77
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	78 IRRef fuseref; /* Fusion limit (loopref, 0 or FUSE_DISABLED). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	79 IRRef sectref; /* Section base reference (loopref or 0). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	80 IRRef loopref; /* Reference of LOOP instruction (or 0). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	81
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	82 BCReg topslot; /* Number of slots for stack check (unless 0). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	83 int32_t gcsteps; /* Accumulated number of GC steps (per section). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	84
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	85 GCtrace T; / Trace to assemble. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	86 GCtrace parent; / Parent trace (or NULL). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	87
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	88 MCode mcbot; / Bottom of reserved MCode. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	89 MCode mctop; / Top of generated MCode. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	90 MCode mctoporig; / Original top of generated MCode. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	91 MCode mcloop; / Pointer to loop MCode (or NULL). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	92 MCode invmcp; / Points to invertible loop branch (or NULL). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	93 MCode flagmcp; / Pending opportunity to merge flag setting ins. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	94 MCode realign; / Realign loop if not NULL. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	95
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	96 #ifdef RID_NUM_KREF
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	97 intptr_t krefk[RID_NUM_KREF];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	98 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	99 IRRef1 phireg[RID_MAX]; /* PHI register references. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	100 uint16_t parentmap[LJ_MAX_JSLOTS]; /* Parent instruction to RegSP map. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	101 } ASMState;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	102
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	103 #ifdef LUA_USE_ASSERT
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	104 #define lj_assertA(c, ...) lj_assertG_(J2G(as->J), (c), __VA_ARGS__)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	105 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	106 #define lj_assertA(c, ...) ((void)as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	107 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	108
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	109 #define IR(ref) (&as->ir[(ref)])
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	110
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	111 #define ASMREF_TMP1 REF_TRUE /* Temp. register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	112 #define ASMREF_TMP2 REF_FALSE /* Temp. register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	113 #define ASMREF_L REF_NIL /* Stores register for L. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	114
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	115 /* Check for variant to invariant references. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	116 #define iscrossref(as, ref) ((ref) < as->sectref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	117
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	118 /* Inhibit memory op fusion from variant to invariant references. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	119 #define FUSE_DISABLED (~(IRRef)0)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	120 #define mayfuse(as, ref) ((ref) > as->fuseref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	121 #define neverfuse(as) (as->fuseref == FUSE_DISABLED)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	122 #define canfuse(as, ir) (!neverfuse(as) && !irt_isphi((ir)->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	123 #define opisfusableload(o) \
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	124 ((o) == IR_ALOAD \|\| (o) == IR_HLOAD \|\| (o) == IR_ULOAD \|\| \
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	125 (o) == IR_FLOAD \|\| (o) == IR_XLOAD \|\| (o) == IR_SLOAD \|\| (o) == IR_VLOAD)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	126
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	127 /* Sparse limit checks using a red zone before the actual limit. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	128 #define MCLIM_REDZONE 64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	129
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	130 static LJ_NORET LJ_NOINLINE void asm_mclimit(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	131 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	132 lj_mcode_limiterr(as->J, (size_t)(as->mctop - as->mcp + 4*MCLIM_REDZONE));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	133 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	134
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	135 static LJ_AINLINE void checkmclim(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	136 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	137 #ifdef LUA_USE_ASSERT
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	138 if (as->mcp + MCLIM_REDZONE < as->mcp_prev) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	139 IRIns *ir = IR(as->curins+1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	140 lj_assertA(0, "red zone overflow: %p IR %04d %02d %04d %04d\n", as->mcp,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	141 as->curins+1-REF_BIAS, ir->o, ir->op1-REF_BIAS, ir->op2-REF_BIAS);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	142 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	143 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	144 if (LJ_UNLIKELY(as->mcp < as->mclim)) asm_mclimit(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	145 #ifdef LUA_USE_ASSERT
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	146 as->mcp_prev = as->mcp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	147 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	148 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	149
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	150 #ifdef RID_NUM_KREF
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	151 #define ra_iskref(ref) ((ref) < RID_NUM_KREF)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	152 #define ra_krefreg(ref) ((Reg)(RID_MIN_KREF + (Reg)(ref)))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	153 #define ra_krefk(as, ref) (as->krefk[(ref)])
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	154
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	155 static LJ_AINLINE void ra_setkref(ASMState *as, Reg r, intptr_t k)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	156 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	157 IRRef ref = (IRRef)(r - RID_MIN_KREF);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	158 as->krefk[ref] = k;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	159 as->cost[r] = REGCOST(ref, ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	160 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	161
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	162 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	163 #define ra_iskref(ref) 0
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	164 #define ra_krefreg(ref) RID_MIN_GPR
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	165 #define ra_krefk(as, ref) 0
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	166 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	167
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	168 /* Arch-specific field offsets. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	169 static const uint8_t field_ofs[IRFL__MAX+1] = {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	170 #define FLOFS(name, ofs) (uint8_t)(ofs),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	171 IRFLDEF(FLOFS)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	172 #undef FLOFS
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	173 0
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	174 };
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	175
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	176 /* -- Target-specific instruction emitter --------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	177
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	178 #if LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	179 #include "lj_emit_x86.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	180 #elif LJ_TARGET_ARM
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	181 #include "lj_emit_arm.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	182 #elif LJ_TARGET_ARM64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	183 #include "lj_emit_arm64.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	184 #elif LJ_TARGET_PPC
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	185 #include "lj_emit_ppc.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	186 #elif LJ_TARGET_MIPS
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	187 #include "lj_emit_mips.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	188 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	189 #error "Missing instruction emitter for target CPU"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	190 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	191
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	192 /* Generic load/store of register from/to stack slot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	193 #define emit_spload(as, ir, r, ofs) \
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	194 emit_loadofs(as, ir, (r), RID_SP, (ofs))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	195 #define emit_spstore(as, ir, r, ofs) \
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	196 emit_storeofs(as, ir, (r), RID_SP, (ofs))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	197
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	198 /* -- Register allocator debugging ---------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	199
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	200 /* #define LUAJIT_DEBUG_RA */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	201
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	202 #ifdef LUAJIT_DEBUG_RA
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	203
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	204 #include <stdio.h>
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	205 #include <stdarg.h>
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	206
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	207 #define RIDNAME(name) #name,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	208 static const char *const ra_regname[] = {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	209 GPRDEF(RIDNAME)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	210 FPRDEF(RIDNAME)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	211 VRIDDEF(RIDNAME)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	212 NULL
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	213 };
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	214 #undef RIDNAME
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	215
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	216 static char ra_dbg_buf[65536];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	217 static char *ra_dbg_p;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	218 static char *ra_dbg_merge;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	219 static MCode *ra_dbg_mcp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	220
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	221 static void ra_dstart(void)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	222 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	223 ra_dbg_p = ra_dbg_buf;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	224 ra_dbg_merge = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	225 ra_dbg_mcp = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	226 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	227
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	228 static void ra_dflush(void)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	229 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	230 fwrite(ra_dbg_buf, 1, (size_t)(ra_dbg_p-ra_dbg_buf), stdout);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	231 ra_dstart();
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	232 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	233
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	234 static void ra_dprintf(ASMState as, const char fmt, ...)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	235 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	236 char *p;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	237 va_list argp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	238 va_start(argp, fmt);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	239 p = ra_dbg_mcp == as->mcp ? ra_dbg_merge : ra_dbg_p;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	240 ra_dbg_mcp = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	241 p += sprintf(p, "%08x \e[36m%04d ", (uintptr_t)as->mcp, as->curins-REF_BIAS);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	242 for (;;) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	243 const char *e = strchr(fmt, '$');
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	244 if (e == NULL) break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	245 memcpy(p, fmt, (size_t)(e-fmt));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	246 p += e-fmt;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	247 if (e[1] == 'r') {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	248 Reg r = va_arg(argp, Reg) & RID_MASK;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	249 if (r <= RID_MAX) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	250 const char *q;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	251 for (q = ra_regname[r]; *q; q++)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	252 p++ = q >= 'A' && q <= 'Z' ? q + 0x20 : *q;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	253 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	254 *p++ = '?';
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	255 lj_assertA(0, "bad register %d for debug format \"%s\"", r, fmt);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	256 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	257 } else if (e[1] == 'f' \|\| e[1] == 'i') {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	258 IRRef ref;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	259 if (e[1] == 'f')
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	260 ref = va_arg(argp, IRRef);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	261 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	262 ref = va_arg(argp, IRIns *) - as->ir;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	263 if (ref >= REF_BIAS)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	264 p += sprintf(p, "%04d", ref - REF_BIAS);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	265 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	266 p += sprintf(p, "K%03d", REF_BIAS - ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	267 } else if (e[1] == 's') {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	268 uint32_t slot = va_arg(argp, uint32_t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	269 p += sprintf(p, "[sp+0x%x]", sps_scale(slot));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	270 } else if (e[1] == 'x') {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	271 p += sprintf(p, "%08x", va_arg(argp, int32_t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	272 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	273 lj_assertA(0, "bad debug format code");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	274 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	275 fmt = e+2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	276 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	277 va_end(argp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	278 while (*fmt)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	279 p++ = fmt++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	280 p++ = '\e'; p++ = '['; p++ = 'm'; p++ = '\n';
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	281 if (p > ra_dbg_buf+sizeof(ra_dbg_buf)-256) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	282 fwrite(ra_dbg_buf, 1, (size_t)(p-ra_dbg_buf), stdout);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	283 p = ra_dbg_buf;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	284 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	285 ra_dbg_p = p;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	286 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	287
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	288 #define RA_DBG_START() ra_dstart()
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	289 #define RA_DBG_FLUSH() ra_dflush()
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	290 #define RA_DBG_REF() \
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	291 do { char *_p = ra_dbg_p; ra_dprintf(as, ""); \
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	292 ra_dbg_merge = _p; ra_dbg_mcp = as->mcp; } while (0)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	293 #define RA_DBGX(x) ra_dprintf x
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	294
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	295 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	296 #define RA_DBG_START() ((void)0)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	297 #define RA_DBG_FLUSH() ((void)0)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	298 #define RA_DBG_REF() ((void)0)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	299 #define RA_DBGX(x) ((void)0)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	300 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	301
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	302 /* -- Register allocator -------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	303
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	304 #define ra_free(as, r) rset_set(as->freeset, (r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	305 #define ra_modified(as, r) rset_set(as->modset, (r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	306 #define ra_weak(as, r) rset_set(as->weakset, (r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	307 #define ra_noweak(as, r) rset_clear(as->weakset, (r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	308
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	309 #define ra_used(ir) (ra_hasreg((ir)->r) \|\| ra_hasspill((ir)->s))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	310
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	311 /* Setup register allocator. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	312 static void ra_setup(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	313 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	314 Reg r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	315 /* Initially all regs (except the stack pointer) are free for use. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	316 as->freeset = RSET_INIT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	317 as->modset = RSET_EMPTY;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	318 as->weakset = RSET_EMPTY;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	319 as->phiset = RSET_EMPTY;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	320 memset(as->phireg, 0, sizeof(as->phireg));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	321 for (r = RID_MIN_GPR; r < RID_MAX; r++)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	322 as->cost[r] = REGCOST(~0u, 0u);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	323 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	324
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	325 /* Rematerialize constants. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	326 static Reg ra_rematk(ASMState *as, IRRef ref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	327 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	328 IRIns *ir;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	329 Reg r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	330 if (ra_iskref(ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	331 r = ra_krefreg(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	332 lj_assertA(!rset_test(as->freeset, r), "rematk of free reg %d", r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	333 ra_free(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	334 ra_modified(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	335 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	336 emit_loadu64(as, r, ra_krefk(as, ref));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	337 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	338 emit_loadi(as, r, ra_krefk(as, ref));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	339 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	340 return r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	341 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	342 ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	343 r = ir->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	344 lj_assertA(ra_hasreg(r), "rematk of K%03d has no reg", REF_BIAS - ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	345 lj_assertA(!ra_hasspill(ir->s),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	346 "rematk of K%03d has spill slot [%x]", REF_BIAS - ref, ir->s);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	347 ra_free(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	348 ra_modified(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	349 ir->r = RID_INIT; /* Do not keep any hint. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	350 RA_DBGX((as, "remat $i $r", ir, r));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	351 #if !LJ_SOFTFP32
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	352 if (ir->o == IR_KNUM) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	353 emit_loadk64(as, r, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	354 } else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	355 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	356 if (emit_canremat(REF_BASE) && ir->o == IR_BASE) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	357 ra_sethint(ir->r, RID_BASE); /* Restore BASE register hint. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	358 emit_getgl(as, r, jit_base);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	359 } else if (emit_canremat(ASMREF_L) && ir->o == IR_KPRI) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	360 /* REF_NIL stores ASMREF_L register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	361 lj_assertA(irt_isnil(ir->t), "rematk of bad ASMREF_L");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	362 emit_getgl(as, r, cur_L);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	363 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	364 } else if (ir->o == IR_KINT64) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	365 emit_loadu64(as, r, ir_kint64(ir)->u64);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	366 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	367 } else if (ir->o == IR_KGC) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	368 emit_loadu64(as, r, (uintptr_t)ir_kgc(ir));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	369 } else if (ir->o == IR_KPTR \|\| ir->o == IR_KKPTR) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	370 emit_loadu64(as, r, (uintptr_t)ir_kptr(ir));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	371 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	372 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	373 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	374 lj_assertA(ir->o == IR_KINT \|\| ir->o == IR_KGC \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	375 ir->o == IR_KPTR \|\| ir->o == IR_KKPTR \|\| ir->o == IR_KNULL,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	376 "rematk of bad IR op %d", ir->o);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	377 emit_loadi(as, r, ir->i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	378 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	379 return r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	380 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	381
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	382 /* Force a spill. Allocate a new spill slot if needed. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	383 static int32_t ra_spill(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	384 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	385 int32_t slot = ir->s;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	386 lj_assertA(ir >= as->ir + REF_TRUE,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	387 "spill of K%03d", REF_BIAS - (int)(ir - as->ir));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	388 if (!ra_hasspill(slot)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	389 if (irt_is64(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	390 slot = as->evenspill;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	391 as->evenspill += 2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	392 } else if (as->oddspill) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	393 slot = as->oddspill;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	394 as->oddspill = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	395 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	396 slot = as->evenspill;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	397 as->oddspill = slot+1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	398 as->evenspill += 2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	399 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	400 if (as->evenspill > 256)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	401 lj_trace_err(as->J, LJ_TRERR_SPILLOV);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	402 ir->s = (uint8_t)slot;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	403 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	404 return sps_scale(slot);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	405 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	406
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	407 /* Release the temporarily allocated register in ASMREF_TMP1/ASMREF_TMP2. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	408 static Reg ra_releasetmp(ASMState *as, IRRef ref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	409 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	410 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	411 Reg r = ir->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	412 lj_assertA(ra_hasreg(r), "release of TMP%d has no reg", ref-ASMREF_TMP1+1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	413 lj_assertA(!ra_hasspill(ir->s),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	414 "release of TMP%d has spill slot [%x]", ref-ASMREF_TMP1+1, ir->s);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	415 ra_free(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	416 ra_modified(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	417 ir->r = RID_INIT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	418 return r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	419 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	420
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	421 /* Restore a register (marked as free). Rematerialize or force a spill. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	422 static Reg ra_restore(ASMState *as, IRRef ref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	423 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	424 if (emit_canremat(ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	425 return ra_rematk(as, ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	426 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	427 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	428 int32_t ofs = ra_spill(as, ir); /* Force a spill slot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	429 Reg r = ir->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	430 lj_assertA(ra_hasreg(r), "restore of IR %04d has no reg", ref - REF_BIAS);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	431 ra_sethint(ir->r, r); /* Keep hint. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	432 ra_free(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	433 if (!rset_test(as->weakset, r)) { /* Only restore non-weak references. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	434 ra_modified(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	435 RA_DBGX((as, "restore $i $r", ir, r));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	436 emit_spload(as, ir, r, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	437 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	438 return r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	439 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	440 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	441
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	442 /* Save a register to a spill slot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	443 static void ra_save(ASMState as, IRIns ir, Reg r)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	444 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	445 RA_DBGX((as, "save $i $r", ir, r));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	446 emit_spstore(as, ir, r, sps_scale(ir->s));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	447 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	448
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	449 #define MINCOST(name) \
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	450 if (rset_test(RSET_ALL, RID_##name) && \
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	451 LJ_LIKELY(allow&RID2RSET(RID_##name)) && as->cost[RID_##name] < cost) \
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	452 cost = as->cost[RID_##name];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	453
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	454 /* Evict the register with the lowest cost, forcing a restore. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	455 static Reg ra_evict(ASMState *as, RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	456 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	457 IRRef ref;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	458 RegCost cost = ~(RegCost)0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	459 lj_assertA(allow != RSET_EMPTY, "evict from empty set");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	460 if (RID_NUM_FPR == 0 \|\| allow < RID2RSET(RID_MAX_GPR)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	461 GPRDEF(MINCOST)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	462 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	463 FPRDEF(MINCOST)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	464 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	465 ref = regcost_ref(cost);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	466 lj_assertA(ra_iskref(ref) \|\| (ref >= as->T->nk && ref < as->T->nins),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	467 "evict of out-of-range IR %04d", ref - REF_BIAS);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	468 /* Preferably pick any weak ref instead of a non-weak, non-const ref. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	469 if (!irref_isk(ref) && (as->weakset & allow)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	470 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	471 if (!rset_test(as->weakset, ir->r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	472 ref = regcost_ref(as->cost[rset_pickbot((as->weakset & allow))]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	473 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	474 return ra_restore(as, ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	475 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	476
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	477 /* Pick any register (marked as free). Evict on-demand. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	478 static Reg ra_pick(ASMState *as, RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	479 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	480 RegSet pick = as->freeset & allow;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	481 if (!pick)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	482 return ra_evict(as, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	483 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	484 return rset_picktop(pick);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	485 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	486
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	487 /* Get a scratch register (marked as free). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	488 static Reg ra_scratch(ASMState *as, RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	489 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	490 Reg r = ra_pick(as, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	491 ra_modified(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	492 RA_DBGX((as, "scratch $r", r));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	493 return r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	494 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	495
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	496 /* Evict all registers from a set (if not free). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	497 static void ra_evictset(ASMState *as, RegSet drop)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	498 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	499 RegSet work;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	500 as->modset \|= drop;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	501 #if !LJ_SOFTFP
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	502 work = (drop & ~as->freeset) & RSET_FPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	503 while (work) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	504 Reg r = rset_pickbot(work);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	505 ra_restore(as, regcost_ref(as->cost[r]));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	506 rset_clear(work, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	507 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	508 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	509 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	510 work = (drop & ~as->freeset);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	511 while (work) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	512 Reg r = rset_pickbot(work);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	513 ra_restore(as, regcost_ref(as->cost[r]));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	514 rset_clear(work, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	515 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	516 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	517 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	518
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	519 /* Evict (rematerialize) all registers allocated to constants. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	520 static void ra_evictk(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	521 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	522 RegSet work;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	523 #if !LJ_SOFTFP
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	524 work = ~as->freeset & RSET_FPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	525 while (work) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	526 Reg r = rset_pickbot(work);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	527 IRRef ref = regcost_ref(as->cost[r]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	528 if (emit_canremat(ref) && irref_isk(ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	529 ra_rematk(as, ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	530 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	531 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	532 rset_clear(work, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	533 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	534 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	535 work = ~as->freeset & RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	536 while (work) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	537 Reg r = rset_pickbot(work);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	538 IRRef ref = regcost_ref(as->cost[r]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	539 if (emit_canremat(ref) && irref_isk(ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	540 ra_rematk(as, ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	541 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	542 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	543 rset_clear(work, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	544 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	545 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	546
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	547 #ifdef RID_NUM_KREF
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	548 /* Allocate a register for a constant. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	549 static Reg ra_allock(ASMState *as, intptr_t k, RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	550 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	551 /* First try to find a register which already holds the same constant. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	552 RegSet pick, work = ~as->freeset & RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	553 Reg r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	554 while (work) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	555 IRRef ref;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	556 r = rset_pickbot(work);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	557 ref = regcost_ref(as->cost[r]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	558 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	559 if (ref < ASMREF_L) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	560 if (ra_iskref(ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	561 if (k == ra_krefk(as, ref))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	562 return r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	563 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	564 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	565 if ((ir->o == IR_KINT64 && k == (int64_t)ir_kint64(ir)->u64) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	566 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	567 (ir->o == IR_KINT && k == ir->i) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	568 (ir->o == IR_KGC && k == (intptr_t)ir_kgc(ir)) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	569 ((ir->o == IR_KPTR \|\| ir->o == IR_KKPTR) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	570 k == (intptr_t)ir_kptr(ir))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	571 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	572 (ir->o != IR_KINT64 && k == ir->i)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	573 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	574 )
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	575 return r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	576 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	577 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	578 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	579 if (ref < ASMREF_L &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	580 k == (ra_iskref(ref) ? ra_krefk(as, ref) : IR(ref)->i))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	581 return r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	582 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	583 rset_clear(work, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	584 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	585 pick = as->freeset & allow;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	586 if (pick) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	587 /* Constants should preferably get unmodified registers. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	588 if ((pick & ~as->modset))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	589 pick &= ~as->modset;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	590 r = rset_pickbot(pick); /* Reduce conflicts with inverse allocation. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	591 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	592 r = ra_evict(as, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	593 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	594 RA_DBGX((as, "allock $x $r", k, r));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	595 ra_setkref(as, r, k);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	596 rset_clear(as->freeset, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	597 ra_noweak(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	598 return r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	599 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	600
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	601 /* Allocate a specific register for a constant. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	602 static void ra_allockreg(ASMState *as, intptr_t k, Reg r)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	603 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	604 Reg kr = ra_allock(as, k, RID2RSET(r));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	605 if (kr != r) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	606 IRIns irdummy;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	607 irdummy.t.irt = IRT_INT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	608 ra_scratch(as, RID2RSET(r));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	609 emit_movrr(as, &irdummy, r, kr);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	610 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	611 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	612 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	613 #define ra_allockreg(as, k, r) emit_loadi(as, (r), (k))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	614 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	615
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	616 /* Allocate a register for ref from the allowed set of registers.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	617 ** Note: this function assumes the ref does NOT have a register yet!
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	618 ** Picks an optimal register, sets the cost and marks the register as non-free.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	619 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	620 static Reg ra_allocref(ASMState *as, IRRef ref, RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	621 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	622 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	623 RegSet pick = as->freeset & allow;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	624 Reg r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	625 lj_assertA(ra_noreg(ir->r),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	626 "IR %04d already has reg %d", ref - REF_BIAS, ir->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	627 if (pick) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	628 /* First check register hint from propagation or PHI. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	629 if (ra_hashint(ir->r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	630 r = ra_gethint(ir->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	631 if (rset_test(pick, r)) /* Use hint register if possible. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	632 goto found;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	633 /* Rematerialization is cheaper than missing a hint. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	634 if (rset_test(allow, r) && emit_canremat(regcost_ref(as->cost[r]))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	635 ra_rematk(as, regcost_ref(as->cost[r]));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	636 goto found;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	637 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	638 RA_DBGX((as, "hintmiss $f $r", ref, r));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	639 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	640 /* Invariants should preferably get unmodified registers. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	641 if (ref < as->loopref && !irt_isphi(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	642 if ((pick & ~as->modset))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	643 pick &= ~as->modset;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	644 r = rset_pickbot(pick); /* Reduce conflicts with inverse allocation. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	645 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	646 /* We've got plenty of regs, so get callee-save regs if possible. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	647 if (RID_NUM_GPR > 8 && (pick & ~RSET_SCRATCH))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	648 pick &= ~RSET_SCRATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	649 r = rset_picktop(pick);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	650 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	651 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	652 r = ra_evict(as, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	653 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	654 found:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	655 RA_DBGX((as, "alloc $f $r", ref, r));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	656 ir->r = (uint8_t)r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	657 rset_clear(as->freeset, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	658 ra_noweak(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	659 as->cost[r] = REGCOST_REF_T(ref, irt_t(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	660 return r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	661 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	662
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	663 /* Allocate a register on-demand. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	664 static Reg ra_alloc1(ASMState *as, IRRef ref, RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	665 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	666 Reg r = IR(ref)->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	667 /* Note: allow is ignored if the register is already allocated. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	668 if (ra_noreg(r)) r = ra_allocref(as, ref, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	669 ra_noweak(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	670 return r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	671 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	672
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	673 /* Add a register rename to the IR. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	674 static void ra_addrename(ASMState *as, Reg down, IRRef ref, SnapNo snapno)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	675 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	676 IRRef ren;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	677 lj_ir_set(as->J, IRT(IR_RENAME, IRT_NIL), ref, snapno);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	678 ren = tref_ref(lj_ir_emit(as->J));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	679 as->J->cur.ir[ren].r = (uint8_t)down;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	680 as->J->cur.ir[ren].s = SPS_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	681 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	682
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	683 /* Rename register allocation and emit move. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	684 static void ra_rename(ASMState *as, Reg down, Reg up)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	685 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	686 IRRef ref = regcost_ref(as->cost[up] = as->cost[down]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	687 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	688 ir->r = (uint8_t)up;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	689 as->cost[down] = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	690 lj_assertA((down < RID_MAX_GPR) == (up < RID_MAX_GPR),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	691 "rename between GPR/FPR %d and %d", down, up);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	692 lj_assertA(!rset_test(as->freeset, down), "rename from free reg %d", down);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	693 lj_assertA(rset_test(as->freeset, up), "rename to non-free reg %d", up);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	694 ra_free(as, down); /* 'down' is free ... */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	695 ra_modified(as, down);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	696 rset_clear(as->freeset, up); /* ... and 'up' is now allocated. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	697 ra_noweak(as, up);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	698 RA_DBGX((as, "rename $f $r $r", regcost_ref(as->cost[up]), down, up));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	699 emit_movrr(as, ir, down, up); /* Backwards codegen needs inverse move. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	700 if (!ra_hasspill(IR(ref)->s)) { /* Add the rename to the IR. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	701 /*
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	702 ** The rename is effective at the subsequent (already emitted) exit
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	703 ** branch. This is for the current snapshot (as->snapno). Except if we
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	704 ** haven't yet allocated any refs for the snapshot (as->snapalloc == 1),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	705 ** then it belongs to the next snapshot.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	706 ** See also the discussion at asm_snap_checkrename().
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	707 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	708 ra_addrename(as, down, ref, as->snapno + as->snapalloc);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	709 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	710 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	711
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	712 /* Pick a destination register (marked as free).
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	713 ** Caveat: allow is ignored if there's already a destination register.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	714 ** Use ra_destreg() to get a specific register.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	715 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	716 static Reg ra_dest(ASMState as, IRIns ir, RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	717 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	718 Reg dest = ir->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	719 if (ra_hasreg(dest)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	720 ra_free(as, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	721 ra_modified(as, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	722 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	723 if (ra_hashint(dest) && rset_test((as->freeset&allow), ra_gethint(dest))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	724 dest = ra_gethint(dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	725 ra_modified(as, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	726 RA_DBGX((as, "dest $r", dest));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	727 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	728 dest = ra_scratch(as, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	729 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	730 ir->r = dest;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	731 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	732 if (LJ_UNLIKELY(ra_hasspill(ir->s))) ra_save(as, ir, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	733 return dest;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	734 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	735
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	736 /* Force a specific destination register (marked as free). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	737 static void ra_destreg(ASMState as, IRIns ir, Reg r)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	738 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	739 Reg dest = ra_dest(as, ir, RID2RSET(r));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	740 if (dest != r) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	741 lj_assertA(rset_test(as->freeset, r), "dest reg %d is not free", r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	742 ra_modified(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	743 emit_movrr(as, ir, dest, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	744 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	745 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	746
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	747 #if LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	748 /* Propagate dest register to left reference. Emit moves as needed.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	749 ** This is a required fixup step for all 2-operand machine instructions.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	750 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	751 static void ra_left(ASMState *as, Reg dest, IRRef lref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	752 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	753 IRIns *ir = IR(lref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	754 Reg left = ir->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	755 if (ra_noreg(left)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	756 if (irref_isk(lref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	757 if (ir->o == IR_KNUM) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	758 /* FP remat needs a load except for +0. Still better than eviction. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	759 if (tvispzero(ir_knum(ir)) \|\| !(as->freeset & RSET_FPR)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	760 emit_loadk64(as, dest, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	761 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	762 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	763 #if LJ_64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	764 } else if (ir->o == IR_KINT64) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	765 emit_loadk64(as, dest, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	766 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	767 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	768 } else if (ir->o == IR_KGC \|\| ir->o == IR_KPTR \|\| ir->o == IR_KKPTR) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	769 emit_loadk64(as, dest, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	770 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	771 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	772 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	773 } else if (ir->o != IR_KPRI) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	774 lj_assertA(ir->o == IR_KINT \|\| ir->o == IR_KGC \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	775 ir->o == IR_KPTR \|\| ir->o == IR_KKPTR \|\| ir->o == IR_KNULL,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	776 "K%03d has bad IR op %d", REF_BIAS - lref, ir->o);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	777 emit_loadi(as, dest, ir->i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	778 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	779 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	780 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	781 if (!ra_hashint(left) && !iscrossref(as, lref))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	782 ra_sethint(ir->r, dest); /* Propagate register hint. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	783 left = ra_allocref(as, lref, dest < RID_MAX_GPR ? RSET_GPR : RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	784 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	785 ra_noweak(as, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	786 /* Move needed for true 3-operand instruction: y=a+b ==> y=a; y+=b. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	787 if (dest != left) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	788 /* Use register renaming if dest is the PHI reg. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	789 if (irt_isphi(ir->t) && as->phireg[dest] == lref) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	790 ra_modified(as, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	791 ra_rename(as, left, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	792 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	793 emit_movrr(as, ir, dest, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	794 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	795 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	796 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	797 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	798 /* Similar to ra_left, except we override any hints. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	799 static void ra_leftov(ASMState *as, Reg dest, IRRef lref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	800 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	801 IRIns *ir = IR(lref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	802 Reg left = ir->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	803 if (ra_noreg(left)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	804 ra_sethint(ir->r, dest); /* Propagate register hint. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	805 left = ra_allocref(as, lref,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	806 (LJ_SOFTFP \|\| dest < RID_MAX_GPR) ? RSET_GPR : RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	807 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	808 ra_noweak(as, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	809 if (dest != left) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	810 /* Use register renaming if dest is the PHI reg. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	811 if (irt_isphi(ir->t) && as->phireg[dest] == lref) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	812 ra_modified(as, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	813 ra_rename(as, left, dest);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	814 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	815 emit_movrr(as, ir, dest, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	816 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	817 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	818 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	819 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	820
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	821 /* Force a RID_RETLO/RID_RETHI destination register pair (marked as free). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	822 static void ra_destpair(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	823 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	824 Reg destlo = ir->r, desthi = (ir+1)->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	825 IRIns *irx = (LJ_64 && !irt_is64(ir->t)) ? ir+1 : ir;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	826 /* First spill unrelated refs blocking the destination registers. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	827 if (!rset_test(as->freeset, RID_RETLO) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	828 destlo != RID_RETLO && desthi != RID_RETLO)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	829 ra_restore(as, regcost_ref(as->cost[RID_RETLO]));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	830 if (!rset_test(as->freeset, RID_RETHI) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	831 destlo != RID_RETHI && desthi != RID_RETHI)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	832 ra_restore(as, regcost_ref(as->cost[RID_RETHI]));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	833 /* Next free the destination registers (if any). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	834 if (ra_hasreg(destlo)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	835 ra_free(as, destlo);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	836 ra_modified(as, destlo);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	837 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	838 destlo = RID_RETLO;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	839 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	840 if (ra_hasreg(desthi)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	841 ra_free(as, desthi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	842 ra_modified(as, desthi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	843 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	844 desthi = RID_RETHI;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	845 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	846 /* Check for conflicts and shuffle the registers as needed. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	847 if (destlo == RID_RETHI) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	848 if (desthi == RID_RETLO) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	849 #if LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	850 *--as->mcp = XI_XCHGa + RID_RETHI;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	851 if (LJ_64 && irt_is64(irx->t)) *--as->mcp = 0x48;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	852 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	853 emit_movrr(as, irx, RID_RETHI, RID_TMP);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	854 emit_movrr(as, irx, RID_RETLO, RID_RETHI);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	855 emit_movrr(as, irx, RID_TMP, RID_RETLO);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	856 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	857 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	858 emit_movrr(as, irx, RID_RETHI, RID_RETLO);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	859 if (desthi != RID_RETHI) emit_movrr(as, irx, desthi, RID_RETHI);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	860 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	861 } else if (desthi == RID_RETLO) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	862 emit_movrr(as, irx, RID_RETLO, RID_RETHI);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	863 if (destlo != RID_RETLO) emit_movrr(as, irx, destlo, RID_RETLO);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	864 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	865 if (desthi != RID_RETHI) emit_movrr(as, irx, desthi, RID_RETHI);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	866 if (destlo != RID_RETLO) emit_movrr(as, irx, destlo, RID_RETLO);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	867 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	868 /* Restore spill slots (if any). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	869 if (ra_hasspill((ir+1)->s)) ra_save(as, ir+1, RID_RETHI);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	870 if (ra_hasspill(ir->s)) ra_save(as, ir, RID_RETLO);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	871 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	872
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	873 /* -- Snapshot handling --------- ----------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	874
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	875 /* Can we rematerialize a KNUM instead of forcing a spill? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	876 static int asm_snap_canremat(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	877 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	878 Reg r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	879 for (r = RID_MIN_FPR; r < RID_MAX_FPR; r++)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	880 if (irref_isk(regcost_ref(as->cost[r])))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	881 return 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	882 return 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	883 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	884
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	885 /* Check whether a sunk store corresponds to an allocation. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	886 static int asm_sunk_store(ASMState as, IRIns ira, IRIns *irs)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	887 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	888 if (irs->s == 255) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	889 if (irs->o == IR_ASTORE \|\| irs->o == IR_HSTORE \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	890 irs->o == IR_FSTORE \|\| irs->o == IR_XSTORE) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	891 IRIns *irk = IR(irs->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	892 if (irk->o == IR_AREF \|\| irk->o == IR_HREFK)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	893 irk = IR(irk->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	894 return (IR(irk->op1) == ira);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	895 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	896 return 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	897 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	898 return (ira + irs->s == irs); /* Quick check. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	899 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	900 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	901
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	902 /* Allocate register or spill slot for a ref that escapes to a snapshot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	903 static void asm_snap_alloc1(ASMState *as, IRRef ref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	904 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	905 IRIns *ir = IR(ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	906 if (!irref_isk(ref) && ir->r != RID_SUNK) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	907 bloomset(as->snapfilt1, ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	908 bloomset(as->snapfilt2, hashrot(ref, ref + HASH_BIAS));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	909 if (ra_used(ir)) return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	910 if (ir->r == RID_SINK) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	911 ir->r = RID_SUNK;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	912 #if LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	913 if (ir->o == IR_CNEWI) { /* Allocate CNEWI value. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	914 asm_snap_alloc1(as, ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	915 if (LJ_32 && (ir+1)->o == IR_HIOP)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	916 asm_snap_alloc1(as, (ir+1)->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	917 } else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	918 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	919 { /* Allocate stored values for TNEW, TDUP and CNEW. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	920 IRIns *irs;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	921 lj_assertA(ir->o == IR_TNEW \|\| ir->o == IR_TDUP \|\| ir->o == IR_CNEW,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	922 "sink of IR %04d has bad op %d", ref - REF_BIAS, ir->o);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	923 for (irs = IR(as->snapref-1); irs > ir; irs--)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	924 if (irs->r == RID_SINK && asm_sunk_store(as, ir, irs)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	925 lj_assertA(irs->o == IR_ASTORE \|\| irs->o == IR_HSTORE \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	926 irs->o == IR_FSTORE \|\| irs->o == IR_XSTORE,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	927 "sunk store IR %04d has bad op %d",
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	928 (int)(irs - as->ir) - REF_BIAS, irs->o);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	929 asm_snap_alloc1(as, irs->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	930 if (LJ_32 && (irs+1)->o == IR_HIOP)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	931 asm_snap_alloc1(as, (irs+1)->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	932 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	933 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	934 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	935 RegSet allow;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	936 if (ir->o == IR_CONV && ir->op2 == IRCONV_NUM_INT) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	937 IRIns *irc;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	938 for (irc = IR(as->curins); irc > ir; irc--)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	939 if ((irc->op1 == ref \|\| irc->op2 == ref) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	940 !(irc->r == RID_SINK \|\| irc->r == RID_SUNK))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	941 goto nosink; /* Don't sink conversion if result is used. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	942 asm_snap_alloc1(as, ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	943 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	944 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	945 nosink:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	946 allow = (!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	947 if ((as->freeset & allow) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	948 (allow == RSET_FPR && asm_snap_canremat(as))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	949 /* Get a weak register if we have a free one or can rematerialize. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	950 Reg r = ra_allocref(as, ref, allow); /* Allocate a register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	951 if (!irt_isphi(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	952 ra_weak(as, r); /* But mark it as weakly referenced. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	953 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	954 RA_DBGX((as, "snapreg $f $r", ref, ir->r));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	955 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	956 ra_spill(as, ir); /* Otherwise force a spill slot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	957 RA_DBGX((as, "snapspill $f $s", ref, ir->s));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	958 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	959 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	960 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	961 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	962
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	963 /* Allocate refs escaping to a snapshot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	964 static void asm_snap_alloc(ASMState *as, int snapno)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	965 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	966 SnapShot *snap = &as->T->snap[snapno];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	967 SnapEntry *map = &as->T->snapmap[snap->mapofs];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	968 MSize n, nent = snap->nent;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	969 as->snapfilt1 = as->snapfilt2 = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	970 for (n = 0; n < nent; n++) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	971 SnapEntry sn = map[n];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	972 IRRef ref = snap_ref(sn);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	973 if (!irref_isk(ref)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	974 asm_snap_alloc1(as, ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	975 if (LJ_SOFTFP && (sn & SNAP_SOFTFPNUM)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	976 lj_assertA(irt_type(IR(ref+1)->t) == IRT_SOFTFP,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	977 "snap %d[%d] points to bad SOFTFP IR %04d",
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	978 snapno, n, ref - REF_BIAS);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	979 asm_snap_alloc1(as, ref+1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	980 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	981 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	982 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	983 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	984
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	985 /* All guards for a snapshot use the same exitno. This is currently the
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	986 ** same as the snapshot number. Since the exact origin of the exit cannot
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	987 ** be determined, all guards for the same snapshot must exit with the same
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	988 ** RegSP mapping.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	989 ** A renamed ref which has been used in a prior guard for the same snapshot
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	990 ** would cause an inconsistency. The easy way out is to force a spill slot.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	991 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	992 static int asm_snap_checkrename(ASMState *as, IRRef ren)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	993 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	994 if (bloomtest(as->snapfilt1, ren) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	995 bloomtest(as->snapfilt2, hashrot(ren, ren + HASH_BIAS))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	996 IRIns *ir = IR(ren);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	997 ra_spill(as, ir); /* Register renamed, so force a spill slot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	998 RA_DBGX((as, "snaprensp $f $s", ren, ir->s));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	999 return 1; /* Found. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1000 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1001 return 0; /* Not found. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1002 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1003
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1004 /* Prepare snapshot for next guard or throwing instruction. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1005 static void asm_snap_prep(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1006 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1007 if (as->snapalloc) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1008 /* Alloc on first invocation for each snapshot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1009 as->snapalloc = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1010 asm_snap_alloc(as, as->snapno);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1011 as->snaprename = as->T->nins;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1012 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1013 /* Check any renames above the highwater mark. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1014 for (; as->snaprename < as->T->nins; as->snaprename++) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1015 IRIns *ir = &as->T->ir[as->snaprename];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1016 if (asm_snap_checkrename(as, ir->op1))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1017 ir->op2 = REF_BIAS-1; /* Kill rename. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1018 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1019 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1020 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1021
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1022 /* Move to previous snapshot when we cross the current snapshot ref. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1023 static void asm_snap_prev(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1024 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1025 if (as->curins < as->snapref) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1026 uintptr_t ofs = (uintptr_t)(as->mctoporig - as->mcp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1027 if (ofs >= 0x10000) lj_trace_err(as->J, LJ_TRERR_MCODEOV);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1028 do {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1029 if (as->snapno == 0) return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1030 as->snapno--;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1031 as->snapref = as->T->snap[as->snapno].ref;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1032 as->T->snap[as->snapno].mcofs = (uint16_t)ofs; /* Remember mcode ofs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1033 } while (as->curins < as->snapref); /* May have no ins inbetween. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1034 as->snapalloc = 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1035 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1036 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1037
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1038 /* Fixup snapshot mcode offsetst. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1039 static void asm_snap_fixup_mcofs(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1040 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1041 uint32_t sz = (uint32_t)(as->mctoporig - as->mcp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1042 SnapShot *snap = as->T->snap;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1043 SnapNo i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1044 for (i = as->T->nsnap-1; i > 0; i--) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1045 /* Compute offset from mcode start and store in correct snapshot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1046 snap[i].mcofs = (uint16_t)(sz - snap[i-1].mcofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1047 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1048 snap[0].mcofs = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1049 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1050
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1051 /* -- Miscellaneous helpers ----------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1052
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1053 /* Calculate stack adjustment. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1054 static int32_t asm_stack_adjust(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1055 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1056 if (as->evenspill <= SPS_FIXED)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1057 return 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1058 return sps_scale(sps_align(as->evenspill));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1059 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1060
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1061 /* Must match with hash() in lj_tab.c. /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1062 static uint32_t ir_khash(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1063 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1064 uint32_t lo, hi;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1065 UNUSED(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1066 if (irt_isstr(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1067 return ir_kstr(ir)->sid;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1068 } else if (irt_isnum(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1069 lo = ir_knum(ir)->u32.lo;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1070 hi = ir_knum(ir)->u32.hi << 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1071 } else if (irt_ispri(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1072 lj_assertA(!irt_isnil(ir->t), "hash of nil key");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1073 return irt_type(ir->t)-IRT_FALSE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1074 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1075 lj_assertA(irt_isgcv(ir->t), "hash of bad IR type %d", irt_type(ir->t));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1076 lo = u32ptr(ir_kgc(ir));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1077 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1078 hi = (uint32_t)(u64ptr(ir_kgc(ir)) >> 32) \| (irt_toitype(ir->t) << 15);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1079 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1080 hi = lo + HASH_BIAS;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1081 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1082 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1083 return hashrot(lo, hi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1084 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1085
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1086 /* -- Allocations --------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1087
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1088 static void asm_gencall(ASMState as, const CCallInfo ci, IRRef *args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1089 static void asm_setupresult(ASMState as, IRIns ir, const CCallInfo *ci);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1090
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1091 static void asm_snew(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1092 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1093 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_str_new];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1094 IRRef args[3];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1095 asm_snap_prep(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1096 args[0] = ASMREF_L; /* lua_State L /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1097 args[1] = ir->op1; /* const char str /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1098 args[2] = ir->op2; /* size_t len */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1099 as->gcsteps++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1100 asm_setupresult(as, ir, ci); /* GCstr * */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1101 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1102 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1103
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1104 static void asm_tnew(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1105 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1106 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_tab_new1];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1107 IRRef args[2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1108 asm_snap_prep(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1109 args[0] = ASMREF_L; /* lua_State L /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1110 args[1] = ASMREF_TMP1; /* uint32_t ahsize */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1111 as->gcsteps++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1112 asm_setupresult(as, ir, ci); /* GCtab * */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1113 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1114 ra_allockreg(as, ir->op1 \| (ir->op2 << 24), ra_releasetmp(as, ASMREF_TMP1));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1115 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1116
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1117 static void asm_tdup(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1118 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1119 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_tab_dup];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1120 IRRef args[2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1121 asm_snap_prep(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1122 args[0] = ASMREF_L; /* lua_State L /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1123 args[1] = ir->op1; /* const GCtab kt /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1124 as->gcsteps++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1125 asm_setupresult(as, ir, ci); /* GCtab * */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1126 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1127 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1128
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1129 static void asm_gc_check(ASMState *as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1130
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1131 /* Explicit GC step. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1132 static void asm_gcstep(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1133 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1134 IRIns *ira;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1135 for (ira = IR(as->stopins+1); ira < ir; ira++)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1136 if ((ira->o == IR_TNEW \|\| ira->o == IR_TDUP \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1137 (LJ_HASFFI && (ira->o == IR_CNEW \|\| ira->o == IR_CNEWI))) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1138 ra_used(ira))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1139 as->gcsteps++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1140 if (as->gcsteps)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1141 asm_gc_check(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1142 as->gcsteps = 0x80000000; /* Prevent implicit GC check further up. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1143 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1144
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1145 /* -- Buffer operations --------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1146
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1147 static void asm_tvptr(ASMState *as, Reg dest, IRRef ref, MSize mode);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1148 #if LJ_HASBUFFER
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1149 static void asm_bufhdr_write(ASMState *as, Reg sb);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1150 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1151
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1152 static void asm_bufhdr(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1153 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1154 Reg sb = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1155 switch (ir->op2) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1156 case IRBUFHDR_RESET: {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1157 Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, sb));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1158 IRIns irbp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1159 irbp.ot = IRT(0, IRT_PTR); /* Buffer data pointer type. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1160 emit_storeofs(as, &irbp, tmp, sb, offsetof(SBuf, w));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1161 emit_loadofs(as, &irbp, tmp, sb, offsetof(SBuf, b));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1162 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1163 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1164 case IRBUFHDR_APPEND: {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1165 /* Rematerialize const buffer pointer instead of likely spill. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1166 IRIns *irp = IR(ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1167 if (!(ra_hasreg(irp->r) \|\| irp == ir-1 \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1168 (irp == ir-2 && !ra_used(ir-1)))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1169 while (!(irp->o == IR_BUFHDR && irp->op2 == IRBUFHDR_RESET))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1170 irp = IR(irp->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1171 if (irref_isk(irp->op1)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1172 ra_weak(as, ra_allocref(as, ir->op1, RSET_GPR));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1173 ir = irp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1174 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1175 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1176 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1177 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1178 #if LJ_HASBUFFER
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1179 case IRBUFHDR_WRITE:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1180 asm_bufhdr_write(as, sb);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1181 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1182 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1183 default: lj_assertA(0, "bad BUFHDR op2 %d", ir->op2); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1184 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1185 #if LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1186 ra_left(as, sb, ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1187 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1188 ra_leftov(as, sb, ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1189 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1190 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1191
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1192 static void asm_bufput(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1193 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1194 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_buf_putstr];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1195 IRRef args[3];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1196 IRIns *irs;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1197 int kchar = -129;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1198 args[0] = ir->op1; /* SBuf * */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1199 args[1] = ir->op2; /* GCstr * */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1200 irs = IR(ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1201 lj_assertA(irt_isstr(irs->t),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1202 "BUFPUT of non-string IR %04d", ir->op2 - REF_BIAS);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1203 if (irs->o == IR_KGC) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1204 GCstr *s = ir_kstr(irs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1205 if (s->len == 1) { /* Optimize put of single-char string constant. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1206 kchar = (int8_t)strdata(s)[0]; /* Signed! */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1207 args[1] = ASMREF_TMP1; /* int, truncated to char */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1208 ci = &lj_ir_callinfo[IRCALL_lj_buf_putchar];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1209 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1210 } else if (mayfuse(as, ir->op2) && ra_noreg(irs->r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1211 if (irs->o == IR_TOSTR) { /* Fuse number to string conversions. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1212 if (irs->op2 == IRTOSTR_NUM) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1213 args[1] = ASMREF_TMP1; /* TValue * */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1214 ci = &lj_ir_callinfo[IRCALL_lj_strfmt_putnum];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1215 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1216 lj_assertA(irt_isinteger(IR(irs->op1)->t),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1217 "TOSTR of non-numeric IR %04d", irs->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1218 args[1] = irs->op1; /* int */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1219 if (irs->op2 == IRTOSTR_INT)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1220 ci = &lj_ir_callinfo[IRCALL_lj_strfmt_putint];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1221 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1222 ci = &lj_ir_callinfo[IRCALL_lj_buf_putchar];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1223 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1224 } else if (irs->o == IR_SNEW) { /* Fuse string allocation. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1225 args[1] = irs->op1; /* const void * */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1226 args[2] = irs->op2; /* MSize */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1227 ci = &lj_ir_callinfo[IRCALL_lj_buf_putmem];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1228 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1229 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1230 asm_setupresult(as, ir, ci); /* SBuf * */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1231 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1232 if (args[1] == ASMREF_TMP1) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1233 Reg tmp = ra_releasetmp(as, ASMREF_TMP1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1234 if (kchar == -129)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1235 asm_tvptr(as, tmp, irs->op1, IRTMPREF_IN1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1236 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1237 ra_allockreg(as, kchar, tmp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1238 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1239 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1240
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1241 static void asm_bufstr(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1242 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1243 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_buf_tostr];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1244 IRRef args[1];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1245 args[0] = ir->op1; /* SBuf sb /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1246 as->gcsteps++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1247 asm_setupresult(as, ir, ci); /* GCstr * */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1248 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1249 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1250
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1251 /* -- Type conversions ---------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1252
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1253 static void asm_tostr(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1254 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1255 const CCallInfo *ci;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1256 IRRef args[2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1257 asm_snap_prep(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1258 args[0] = ASMREF_L;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1259 as->gcsteps++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1260 if (ir->op2 == IRTOSTR_NUM) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1261 args[1] = ASMREF_TMP1; /* cTValue * */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1262 ci = &lj_ir_callinfo[IRCALL_lj_strfmt_num];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1263 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1264 args[1] = ir->op1; /* int32_t k */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1265 if (ir->op2 == IRTOSTR_INT)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1266 ci = &lj_ir_callinfo[IRCALL_lj_strfmt_int];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1267 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1268 ci = &lj_ir_callinfo[IRCALL_lj_strfmt_char];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1269 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1270 asm_setupresult(as, ir, ci); /* GCstr * */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1271 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1272 if (ir->op2 == IRTOSTR_NUM)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1273 asm_tvptr(as, ra_releasetmp(as, ASMREF_TMP1), ir->op1, IRTMPREF_IN1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1274 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1275
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1276 #if LJ_32 && LJ_HASFFI && !LJ_SOFTFP && !LJ_TARGET_X86
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1277 static void asm_conv64(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1278 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1279 IRType st = (IRType)((ir-1)->op2 & IRCONV_SRCMASK);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1280 IRType dt = (((ir-1)->op2 & IRCONV_DSTMASK) >> IRCONV_DSH);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1281 IRCallID id;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1282 IRRef args[2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1283 lj_assertA((ir-1)->o == IR_CONV && ir->o == IR_HIOP,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1284 "not a CONV/HIOP pair at IR %04d", (int)(ir - as->ir) - REF_BIAS);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1285 args[LJ_BE] = (ir-1)->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1286 args[LJ_LE] = ir->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1287 if (st == IRT_NUM \|\| st == IRT_FLOAT) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1288 id = IRCALL_fp64_d2l + ((st == IRT_FLOAT) ? 2 : 0) + (dt - IRT_I64);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1289 ir--;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1290 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1291 id = IRCALL_fp64_l2d + ((dt == IRT_FLOAT) ? 2 : 0) + (st - IRT_I64);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1292 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1293 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1294 #if LJ_TARGET_ARM && !LJ_ABI_SOFTFP
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1295 CCallInfo cim = lj_ir_callinfo[id], *ci = &cim;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1296 cim.flags \|= CCI_VARARG; /* These calls don't use the hard-float ABI! */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1297 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1298 const CCallInfo *ci = &lj_ir_callinfo[id];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1299 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1300 asm_setupresult(as, ir, ci);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1301 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1302 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1303 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1304 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1305
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1306 /* -- Memory references --------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1307
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1308 static void asm_newref(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1309 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1310 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_tab_newkey];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1311 IRRef args[3];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1312 if (ir->r == RID_SINK)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1313 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1314 asm_snap_prep(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1315 args[0] = ASMREF_L; /* lua_State L /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1316 args[1] = ir->op1; /* GCtab t /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1317 args[2] = ASMREF_TMP1; /* cTValue key /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1318 asm_setupresult(as, ir, ci); /* TValue * */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1319 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1320 asm_tvptr(as, ra_releasetmp(as, ASMREF_TMP1), ir->op2, IRTMPREF_IN1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1321 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1322
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1323 static void asm_tmpref(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1324 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1325 Reg r = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1326 asm_tvptr(as, r, ir->op1, ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1327 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1328
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1329 static void asm_lref(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1330 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1331 Reg r = ra_dest(as, ir, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1332 #if LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1333 ra_left(as, r, ASMREF_L);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1334 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1335 ra_leftov(as, r, ASMREF_L);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1336 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1337 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1338
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1339 /* -- Calls --------------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1340
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1341 /* Collect arguments from CALL* and CARG instructions. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1342 static void asm_collectargs(ASMState as, IRIns ir,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1343 const CCallInfo ci, IRRef args)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1344 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1345 uint32_t n = CCI_XNARGS(ci);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1346 /* Account for split args. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1347 lj_assertA(n <= CCI_NARGS_MAX*2, "too many args %d to collect", n);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1348 if ((ci->flags & CCI_L)) { *args++ = ASMREF_L; n--; }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1349 while (n-- > 1) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1350 ir = IR(ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1351 lj_assertA(ir->o == IR_CARG, "malformed CALL arg tree");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1352 args[n] = ir->op2 == REF_NIL ? 0 : ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1353 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1354 args[0] = ir->op1 == REF_NIL ? 0 : ir->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1355 lj_assertA(IR(ir->op1)->o != IR_CARG, "malformed CALL arg tree");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1356 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1357
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1358 /* Reconstruct CCallInfo flags for CALLX. /
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1359 static uint32_t asm_callx_flags(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1360 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1361 uint32_t nargs = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1362 if (ir->op1 != REF_NIL) { /* Count number of arguments first. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1363 IRIns *ira = IR(ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1364 nargs++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1365 while (ira->o == IR_CARG) { nargs++; ira = IR(ira->op1); }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1366 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1367 #if LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1368 if (IR(ir->op2)->o == IR_CARG) { /* Copy calling convention info. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1369 CTypeID id = (CTypeID)IR(IR(ir->op2)->op2)->i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1370 CType *ct = ctype_get(ctype_ctsG(J2G(as->J)), id);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1371 nargs \|= ((ct->info & CTF_VARARG) ? CCI_VARARG : 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1372 #if LJ_TARGET_X86
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1373 nargs \|= (ctype_cconv(ct->info) << CCI_CC_SHIFT);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1374 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1375 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1376 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1377 return (nargs \| (ir->t.irt << CCI_OTSHIFT));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1378 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1379
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1380 static void asm_callid(ASMState as, IRIns ir, IRCallID id)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1381 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1382 const CCallInfo *ci = &lj_ir_callinfo[id];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1383 IRRef args[2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1384 args[0] = ir->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1385 args[1] = ir->op2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1386 asm_setupresult(as, ir, ci);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1387 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1388 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1389
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1390 static void asm_call(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1391 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1392 IRRef args[CCI_NARGS_MAX];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1393 const CCallInfo *ci = &lj_ir_callinfo[ir->op2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1394 asm_collectargs(as, ir, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1395 asm_setupresult(as, ir, ci);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1396 asm_gencall(as, ci, args);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1397 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1398
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1399 /* -- PHI and loop handling ----------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1400
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1401 /* Break a PHI cycle by renaming to a free register (evict if needed). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1402 static void asm_phi_break(ASMState *as, RegSet blocked, RegSet blockedby,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1403 RegSet allow)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1404 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1405 RegSet candidates = blocked & allow;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1406 if (candidates) { /* If this register file has candidates. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1407 /* Note: the set for ra_pick cannot be empty, since each register file
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1408 ** has some registers never allocated to PHIs.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1409 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1410 Reg down, up = ra_pick(as, ~blocked & allow); /* Get a free register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1411 if (candidates & ~blockedby) /* Optimize shifts, else it's a cycle. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1412 candidates = candidates & ~blockedby;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1413 down = rset_picktop(candidates); /* Pick candidate PHI register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1414 ra_rename(as, down, up); /* And rename it to the free register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1415 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1416 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1417
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1418 /* PHI register shuffling.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1419 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1420 ** The allocator tries hard to preserve PHI register assignments across
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1421 ** the loop body. Most of the time this loop does nothing, since there
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1422 ** are no register mismatches.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1423 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1424 ** If a register mismatch is detected and ...
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1425 ** - the register is currently free: rename it.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1426 ** - the register is blocked by an invariant: restore/remat and rename it.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1427 ** - Otherwise the register is used by another PHI, so mark it as blocked.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1428 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1429 ** The renames are order-sensitive, so just retry the loop if a register
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1430 ** is marked as blocked, but has been freed in the meantime. A cycle is
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1431 ** detected if all of the blocked registers are allocated. To break the
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1432 ** cycle rename one of them to a free register and retry.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1433 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1434 ** Note that PHI spill slots are kept in sync and don't need to be shuffled.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1435 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1436 static void asm_phi_shuffle(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1437 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1438 RegSet work;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1439
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1440 /* Find and resolve PHI register mismatches. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1441 for (;;) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1442 RegSet blocked = RSET_EMPTY;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1443 RegSet blockedby = RSET_EMPTY;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1444 RegSet phiset = as->phiset;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1445 while (phiset) { /* Check all left PHI operand registers. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1446 Reg r = rset_pickbot(phiset);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1447 IRIns *irl = IR(as->phireg[r]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1448 Reg left = irl->r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1449 if (r != left) { /* Mismatch? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1450 if (!rset_test(as->freeset, r)) { /* PHI register blocked? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1451 IRRef ref = regcost_ref(as->cost[r]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1452 /* Blocked by other PHI (w/reg)? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1453 if (!ra_iskref(ref) && irt_ismarked(IR(ref)->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1454 rset_set(blocked, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1455 if (ra_hasreg(left))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1456 rset_set(blockedby, left);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1457 left = RID_NONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1458 } else { /* Otherwise grab register from invariant. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1459 ra_restore(as, ref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1460 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1461 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1462 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1463 if (ra_hasreg(left)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1464 ra_rename(as, left, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1465 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1466 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1467 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1468 rset_clear(phiset, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1469 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1470 if (!blocked) break; /* Finished. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1471 if (!(as->freeset & blocked)) { /* Break cycles if none are free. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1472 asm_phi_break(as, blocked, blockedby, RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1473 if (!LJ_SOFTFP) asm_phi_break(as, blocked, blockedby, RSET_FPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1474 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1475 } /* Else retry some more renames. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1476 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1477
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1478 /* Restore/remat invariants whose registers are modified inside the loop. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1479 #if !LJ_SOFTFP
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1480 work = as->modset & ~(as->freeset \| as->phiset) & RSET_FPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1481 while (work) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1482 Reg r = rset_pickbot(work);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1483 ra_restore(as, regcost_ref(as->cost[r]));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1484 rset_clear(work, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1485 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1486 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1487 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1488 work = as->modset & ~(as->freeset \| as->phiset);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1489 while (work) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1490 Reg r = rset_pickbot(work);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1491 ra_restore(as, regcost_ref(as->cost[r]));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1492 rset_clear(work, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1493 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1494 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1495
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1496 /* Allocate and save all unsaved PHI regs and clear marks. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1497 work = as->phiset;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1498 while (work) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1499 Reg r = rset_picktop(work);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1500 IRRef lref = as->phireg[r];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1501 IRIns *ir = IR(lref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1502 if (ra_hasspill(ir->s)) { /* Left PHI gained a spill slot? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1503 irt_clearmark(ir->t); /* Handled here, so clear marker now. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1504 ra_alloc1(as, lref, RID2RSET(r));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1505 ra_save(as, ir, r); /* Save to spill slot inside the loop. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1506 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1507 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1508 rset_clear(work, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1509 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1510 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1511
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1512 /* Copy unsynced left/right PHI spill slots. Rarely needed. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1513 static void asm_phi_copyspill(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1514 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1515 int need = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1516 IRIns *ir;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1517 for (ir = IR(as->orignins-1); ir->o == IR_PHI; ir--)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1518 if (ra_hasspill(ir->s) && ra_hasspill(IR(ir->op1)->s))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1519 need \|= irt_isfp(ir->t) ? 2 : 1; /* Unsynced spill slot? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1520 if ((need & 1)) { /* Copy integer spill slots. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1521 #if !LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1522 Reg r = RID_TMP;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1523 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1524 Reg r = RID_RET;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1525 if ((as->freeset & RSET_GPR))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1526 r = rset_pickbot((as->freeset & RSET_GPR));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1527 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1528 emit_spload(as, IR(regcost_ref(as->cost[r])), r, SPOFS_TMP);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1529 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1530 for (ir = IR(as->orignins-1); ir->o == IR_PHI; ir--) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1531 if (ra_hasspill(ir->s)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1532 IRIns *irl = IR(ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1533 if (ra_hasspill(irl->s) && !irt_isfp(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1534 emit_spstore(as, irl, r, sps_scale(irl->s));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1535 emit_spload(as, ir, r, sps_scale(ir->s));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1536 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1537 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1538 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1539 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1540 #if LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1541 if (!rset_test(as->freeset, r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1542 emit_spstore(as, IR(regcost_ref(as->cost[r])), r, SPOFS_TMP);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1543 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1544 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1545 #if !LJ_SOFTFP
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1546 if ((need & 2)) { /* Copy FP spill slots. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1547 #if LJ_TARGET_X86
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1548 Reg r = RID_XMM0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1549 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1550 Reg r = RID_FPRET;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1551 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1552 if ((as->freeset & RSET_FPR))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1553 r = rset_pickbot((as->freeset & RSET_FPR));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1554 if (!rset_test(as->freeset, r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1555 emit_spload(as, IR(regcost_ref(as->cost[r])), r, SPOFS_TMP);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1556 for (ir = IR(as->orignins-1); ir->o == IR_PHI; ir--) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1557 if (ra_hasspill(ir->s)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1558 IRIns *irl = IR(ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1559 if (ra_hasspill(irl->s) && irt_isfp(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1560 emit_spstore(as, irl, r, sps_scale(irl->s));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1561 emit_spload(as, ir, r, sps_scale(ir->s));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1562 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1563 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1564 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1565 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1566 if (!rset_test(as->freeset, r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1567 emit_spstore(as, IR(regcost_ref(as->cost[r])), r, SPOFS_TMP);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1568 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1569 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1570 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1571
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1572 /* Emit renames for left PHIs which are only spilled outside the loop. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1573 static void asm_phi_fixup(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1574 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1575 RegSet work = as->phiset;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1576 while (work) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1577 Reg r = rset_picktop(work);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1578 IRRef lref = as->phireg[r];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1579 IRIns *ir = IR(lref);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1580 if (irt_ismarked(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1581 irt_clearmark(ir->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1582 /* Left PHI gained a spill slot before the loop? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1583 if (ra_hasspill(ir->s)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1584 ra_addrename(as, r, lref, as->loopsnapno);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1585 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1586 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1587 rset_clear(work, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1588 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1589 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1590
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1591 /* Setup right PHI reference. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1592 static void asm_phi(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1593 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1594 RegSet allow = ((!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR) &
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1595 ~as->phiset;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1596 RegSet afree = (as->freeset & allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1597 IRIns *irl = IR(ir->op1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1598 IRIns *irr = IR(ir->op2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1599 if (ir->r == RID_SINK) /* Sink PHI. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1600 return;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1601 /* Spill slot shuffling is not implemented yet (but rarely needed). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1602 if (ra_hasspill(irl->s) \|\| ra_hasspill(irr->s))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1603 lj_trace_err(as->J, LJ_TRERR_NYIPHI);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1604 /* Leave at least one register free for non-PHIs (and PHI cycle breaking). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1605 if ((afree & (afree-1))) { /* Two or more free registers? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1606 Reg r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1607 if (ra_noreg(irr->r)) { /* Get a register for the right PHI. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1608 r = ra_allocref(as, ir->op2, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1609 } else { /* Duplicate right PHI, need a copy (rare). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1610 r = ra_scratch(as, allow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1611 emit_movrr(as, irr, r, irr->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1612 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1613 ir->r = (uint8_t)r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1614 rset_set(as->phiset, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1615 as->phireg[r] = (IRRef1)ir->op1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1616 irt_setmark(irl->t); /* Marks left PHIs _with_ register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1617 if (ra_noreg(irl->r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1618 ra_sethint(irl->r, r); /* Set register hint for left PHI. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1619 } else { /* Otherwise allocate a spill slot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1620 /* This is overly restrictive, but it triggers only on synthetic code. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1621 if (ra_hasreg(irl->r) \|\| ra_hasreg(irr->r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1622 lj_trace_err(as->J, LJ_TRERR_NYIPHI);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1623 ra_spill(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1624 irr->s = ir->s; /* Set right PHI spill slot. Sync left slot later. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1625 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1626 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1627
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1628 static void asm_loop_fixup(ASMState *as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1629
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1630 /* Middle part of a loop. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1631 static void asm_loop(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1632 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1633 MCode *mcspill;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1634 /* LOOP is a guard, so the snapno is up to date. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1635 as->loopsnapno = as->snapno;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1636 if (as->gcsteps)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1637 asm_gc_check(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1638 /* LOOP marks the transition from the variant to the invariant part. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1639 as->flagmcp = as->invmcp = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1640 as->sectref = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1641 if (!neverfuse(as)) as->fuseref = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1642 asm_phi_shuffle(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1643 mcspill = as->mcp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1644 asm_phi_copyspill(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1645 asm_loop_fixup(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1646 as->mcloop = as->mcp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1647 RA_DBGX((as, "===== LOOP ====="));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1648 if (!as->realign) RA_DBG_FLUSH();
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1649 if (as->mcp != mcspill)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1650 emit_jmp(as, mcspill);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1651 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1652
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1653 /* -- Target-specific assembler ------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1654
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1655 #if LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1656 #include "lj_asm_x86.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1657 #elif LJ_TARGET_ARM
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1658 #include "lj_asm_arm.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1659 #elif LJ_TARGET_ARM64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1660 #include "lj_asm_arm64.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1661 #elif LJ_TARGET_PPC
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1662 #include "lj_asm_ppc.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1663 #elif LJ_TARGET_MIPS
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1664 #include "lj_asm_mips.h"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1665 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1666 #error "Missing assembler for target CPU"
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1667 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1668
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1669 /* -- Common instruction helpers ------------------------------------------ */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1670
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1671 #if !LJ_SOFTFP32
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1672 #if !LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1673 #define asm_ldexp(as, ir) asm_callid(as, ir, IRCALL_ldexp)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1674 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1675
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1676 static void asm_pow(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1677 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1678 #if LJ_64 && LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1679 if (!irt_isnum(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1680 asm_callid(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_powi64 :
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1681 IRCALL_lj_carith_powu64);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1682 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1683 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1684 asm_callid(as, ir, IRCALL_pow);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1685 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1686
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1687 static void asm_div(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1688 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1689 #if LJ_64 && LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1690 if (!irt_isnum(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1691 asm_callid(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_divi64 :
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1692 IRCALL_lj_carith_divu64);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1693 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1694 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1695 asm_fpdiv(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1696 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1697 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1698
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1699 static void asm_mod(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1700 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1701 #if LJ_64 && LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1702 if (!irt_isint(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1703 asm_callid(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_modi64 :
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1704 IRCALL_lj_carith_modu64);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1705 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1706 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1707 asm_callid(as, ir, IRCALL_lj_vm_modi);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1708 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1709
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1710 static void asm_fuseequal(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1711 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1712 /* Fuse HREF + EQ/NE. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1713 if ((ir-1)->o == IR_HREF && ir->op1 == as->curins-1) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1714 as->curins--;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1715 asm_href(as, ir-1, (IROp)ir->o);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1716 } else {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1717 asm_equal(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1718 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1719 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1720
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1721 static void asm_alen(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1722 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1723 asm_callid(as, ir, ir->op2 == REF_NIL ? IRCALL_lj_tab_len :
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1724 IRCALL_lj_tab_len_hint);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1725 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1726
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1727 /* -- Instruction dispatch ------------------------------------------------ */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1728
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1729 /* Assemble a single instruction. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1730 static void asm_ir(ASMState as, IRIns ir)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1731 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1732 switch ((IROp)ir->o) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1733 /* Miscellaneous ops. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1734 case IR_LOOP: asm_loop(as); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1735 case IR_NOP: case IR_XBAR:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1736 lj_assertA(!ra_used(ir),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1737 "IR %04d not unused", (int)(ir - as->ir) - REF_BIAS);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1738 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1739 case IR_USE:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1740 ra_alloc1(as, ir->op1, irt_isfp(ir->t) ? RSET_FPR : RSET_GPR); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1741 case IR_PHI: asm_phi(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1742 case IR_HIOP: asm_hiop(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1743 case IR_GCSTEP: asm_gcstep(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1744 case IR_PROF: asm_prof(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1745
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1746 /* Guarded assertions. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1747 case IR_LT: case IR_GE: case IR_LE: case IR_GT:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1748 case IR_ULT: case IR_UGE: case IR_ULE: case IR_UGT:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1749 case IR_ABC:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1750 asm_comp(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1751 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1752 case IR_EQ: case IR_NE: asm_fuseequal(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1753
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1754 case IR_RETF: asm_retf(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1755
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1756 /* Bit ops. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1757 case IR_BNOT: asm_bnot(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1758 case IR_BSWAP: asm_bswap(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1759 case IR_BAND: asm_band(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1760 case IR_BOR: asm_bor(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1761 case IR_BXOR: asm_bxor(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1762 case IR_BSHL: asm_bshl(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1763 case IR_BSHR: asm_bshr(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1764 case IR_BSAR: asm_bsar(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1765 case IR_BROL: asm_brol(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1766 case IR_BROR: asm_bror(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1767
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1768 /* Arithmetic ops. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1769 case IR_ADD: asm_add(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1770 case IR_SUB: asm_sub(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1771 case IR_MUL: asm_mul(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1772 case IR_MOD: asm_mod(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1773 case IR_NEG: asm_neg(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1774 #if LJ_SOFTFP32
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1775 case IR_DIV: case IR_POW: case IR_ABS:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1776 case IR_LDEXP: case IR_FPMATH: case IR_TOBIT:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1777 /* Unused for LJ_SOFTFP32. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1778 lj_assertA(0, "IR %04d with unused op %d",
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1779 (int)(ir - as->ir) - REF_BIAS, ir->o);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1780 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1781 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1782 case IR_DIV: asm_div(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1783 case IR_POW: asm_pow(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1784 case IR_ABS: asm_abs(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1785 case IR_LDEXP: asm_ldexp(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1786 case IR_FPMATH: asm_fpmath(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1787 case IR_TOBIT: asm_tobit(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1788 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1789 case IR_MIN: asm_min(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1790 case IR_MAX: asm_max(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1791
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1792 /* Overflow-checking arithmetic ops. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1793 case IR_ADDOV: asm_addov(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1794 case IR_SUBOV: asm_subov(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1795 case IR_MULOV: asm_mulov(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1796
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1797 /* Memory references. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1798 case IR_AREF: asm_aref(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1799 case IR_HREF: asm_href(as, ir, 0); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1800 case IR_HREFK: asm_hrefk(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1801 case IR_NEWREF: asm_newref(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1802 case IR_UREFO: case IR_UREFC: asm_uref(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1803 case IR_FREF: asm_fref(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1804 case IR_TMPREF: asm_tmpref(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1805 case IR_STRREF: asm_strref(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1806 case IR_LREF: asm_lref(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1807
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1808 /* Loads and stores. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1809 case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1810 asm_ahuvload(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1811 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1812 case IR_FLOAD: asm_fload(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1813 case IR_XLOAD: asm_xload(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1814 case IR_SLOAD: asm_sload(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1815 case IR_ALEN: asm_alen(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1816
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1817 case IR_ASTORE: case IR_HSTORE: case IR_USTORE: asm_ahustore(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1818 case IR_FSTORE: asm_fstore(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1819 case IR_XSTORE: asm_xstore(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1820
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1821 /* Allocations. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1822 case IR_SNEW: case IR_XSNEW: asm_snew(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1823 case IR_TNEW: asm_tnew(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1824 case IR_TDUP: asm_tdup(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1825 case IR_CNEW: case IR_CNEWI:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1826 #if LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1827 asm_cnew(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1828 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1829 lj_assertA(0, "IR %04d with unused op %d",
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1830 (int)(ir - as->ir) - REF_BIAS, ir->o);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1831 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1832 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1833
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1834 /* Buffer operations. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1835 case IR_BUFHDR: asm_bufhdr(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1836 case IR_BUFPUT: asm_bufput(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1837 case IR_BUFSTR: asm_bufstr(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1838
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1839 /* Write barriers. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1840 case IR_TBAR: asm_tbar(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1841 case IR_OBAR: asm_obar(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1842
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1843 /* Type conversions. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1844 case IR_CONV: asm_conv(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1845 case IR_TOSTR: asm_tostr(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1846 case IR_STRTO: asm_strto(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1847
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1848 /* Calls. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1849 case IR_CALLA:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1850 as->gcsteps++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1851 /* fallthrough */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1852 case IR_CALLN: case IR_CALLL: case IR_CALLS: asm_call(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1853 case IR_CALLXS: asm_callx(as, ir); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1854 case IR_CARG: break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1855
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1856 default:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1857 setintV(&as->J->errinfo, ir->o);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1858 lj_trace_err_info(as->J, LJ_TRERR_NYIIR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1859 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1860 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1861 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1862
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1863 /* -- Head of trace ------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1864
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1865 /* Head of a root trace. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1866 static void asm_head_root(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1867 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1868 int32_t spadj;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1869 asm_head_root_base(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1870 emit_setvmstate(as, (int32_t)as->T->traceno);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1871 spadj = asm_stack_adjust(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1872 as->T->spadjust = (uint16_t)spadj;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1873 emit_spsub(as, spadj);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1874 /* Root traces assume a checked stack for the starting proto. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1875 as->T->topslot = gcref(as->T->startpt)->pt.framesize;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1876 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1877
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1878 /* Head of a side trace.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1879 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1880 ** The current simplistic algorithm requires that all slots inherited
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1881 ** from the parent are live in a register between pass 2 and pass 3. This
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1882 ** avoids the complexity of stack slot shuffling. But of course this may
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1883 ** overflow the register set in some cases and cause the dreaded error:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1884 ** "NYI: register coalescing too complex". A refined algorithm is needed.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1885 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1886 static void asm_head_side(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1887 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1888 IRRef1 sloadins[RID_MAX];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1889 RegSet allow = RSET_ALL; /* Inverse of all coalesced registers. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1890 RegSet live = RSET_EMPTY; /* Live parent registers. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1891 RegSet pallow = RSET_GPR; /* Registers needed by the parent stack check. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1892 Reg pbase;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1893 IRIns irp = &as->parent->ir[REF_BASE]; / Parent base. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1894 int32_t spadj, spdelta;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1895 int pass2 = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1896 int pass3 = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1897 IRRef i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1898
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1899 if (as->snapno && as->topslot > as->parent->topslot) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1900 /* Force snap #0 alloc to prevent register overwrite in stack check. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1901 asm_snap_alloc(as, 0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1902 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1903 pbase = asm_head_side_base(as, irp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1904 if (pbase != RID_NONE) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1905 rset_clear(allow, pbase);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1906 rset_clear(pallow, pbase);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1907 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1908
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1909 /* Scan all parent SLOADs and collect register dependencies. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1910 for (i = as->stopins; i > REF_BASE; i--) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1911 IRIns *ir = IR(i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1912 RegSP rs;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1913 lj_assertA((ir->o == IR_SLOAD && (ir->op2 & IRSLOAD_PARENT)) \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1914 (LJ_SOFTFP && ir->o == IR_HIOP) \|\| ir->o == IR_PVAL,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1915 "IR %04d has bad parent op %d",
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1916 (int)(ir - as->ir) - REF_BIAS, ir->o);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1917 rs = as->parentmap[i - REF_FIRST];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1918 if (ra_hasreg(ir->r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1919 rset_clear(allow, ir->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1920 if (ra_hasspill(ir->s)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1921 ra_save(as, ir, ir->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1922 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1923 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1924 } else if (ra_hasspill(ir->s)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1925 irt_setmark(ir->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1926 pass2 = 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1927 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1928 if (ir->r == rs) { /* Coalesce matching registers right now. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1929 ra_free(as, ir->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1930 } else if (ra_hasspill(regsp_spill(rs))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1931 if (ra_hasreg(ir->r))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1932 pass3 = 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1933 } else if (ra_used(ir)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1934 sloadins[rs] = (IRRef1)i;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1935 rset_set(live, rs); /* Block live parent register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1936 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1937 if (!ra_hasspill(regsp_spill(rs))) rset_clear(pallow, regsp_reg(rs));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1938 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1939
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1940 /* Calculate stack frame adjustment. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1941 spadj = asm_stack_adjust(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1942 spdelta = spadj - (int32_t)as->parent->spadjust;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1943 if (spdelta < 0) { /* Don't shrink the stack frame. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1944 spadj = (int32_t)as->parent->spadjust;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1945 spdelta = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1946 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1947 as->T->spadjust = (uint16_t)spadj;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1948
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1949 /* Reload spilled target registers. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1950 if (pass2) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1951 for (i = as->stopins; i > REF_BASE; i--) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1952 IRIns *ir = IR(i);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1953 if (irt_ismarked(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1954 RegSet mask;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1955 Reg r;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1956 RegSP rs;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1957 irt_clearmark(ir->t);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1958 rs = as->parentmap[i - REF_FIRST];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1959 if (!ra_hasspill(regsp_spill(rs)))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1960 ra_sethint(ir->r, rs); /* Hint may be gone, set it again. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1961 else if (sps_scale(regsp_spill(rs))+spdelta == sps_scale(ir->s))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1962 continue; /* Same spill slot, do nothing. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1963 mask = ((!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR) & allow;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1964 if (mask == RSET_EMPTY)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1965 lj_trace_err(as->J, LJ_TRERR_NYICOAL);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1966 r = ra_allocref(as, i, mask);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1967 ra_save(as, ir, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1968 rset_clear(allow, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1969 if (r == rs) { /* Coalesce matching registers right now. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1970 ra_free(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1971 rset_clear(live, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1972 } else if (ra_hasspill(regsp_spill(rs))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1973 pass3 = 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1974 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1975 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1976 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1977 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1978 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1979
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1980 /* Store trace number and adjust stack frame relative to the parent. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1981 emit_setvmstate(as, (int32_t)as->T->traceno);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1982 emit_spsub(as, spdelta);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1983
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1984 #if !LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1985 /* Restore BASE register from parent spill slot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1986 if (ra_hasspill(irp->s))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1987 emit_spload(as, IR(REF_BASE), IR(REF_BASE)->r, sps_scale(irp->s));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1988 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1989
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1990 /* Restore target registers from parent spill slots. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1991 if (pass3) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1992 RegSet work = ~as->freeset & RSET_ALL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1993 while (work) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1994 Reg r = rset_pickbot(work);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1995 IRRef ref = regcost_ref(as->cost[r]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1996 RegSP rs = as->parentmap[ref - REF_FIRST];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1997 rset_clear(work, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1998 if (ra_hasspill(regsp_spill(rs))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	1999 int32_t ofs = sps_scale(regsp_spill(rs));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2000 ra_free(as, r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2001 emit_spload(as, IR(ref), r, ofs);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2002 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2003 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2004 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2005 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2006
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2007 /* Shuffle registers to match up target regs with parent regs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2008 for (;;) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2009 RegSet work;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2010
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2011 /* Repeatedly coalesce free live registers by moving to their target. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2012 while ((work = as->freeset & live) != RSET_EMPTY) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2013 Reg rp = rset_pickbot(work);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2014 IRIns *ir = IR(sloadins[rp]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2015 rset_clear(live, rp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2016 rset_clear(allow, rp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2017 ra_free(as, ir->r);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2018 emit_movrr(as, ir, ir->r, rp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2019 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2020 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2021
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2022 /* We're done if no live registers remain. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2023 if (live == RSET_EMPTY)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2024 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2025
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2026 /* Break cycles by renaming one target to a temp. register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2027 if (live & RSET_GPR) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2028 RegSet tmpset = as->freeset & ~live & allow & RSET_GPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2029 if (tmpset == RSET_EMPTY)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2030 lj_trace_err(as->J, LJ_TRERR_NYICOAL);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2031 ra_rename(as, rset_pickbot(live & RSET_GPR), rset_pickbot(tmpset));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2032 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2033 if (!LJ_SOFTFP && (live & RSET_FPR)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2034 RegSet tmpset = as->freeset & ~live & allow & RSET_FPR;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2035 if (tmpset == RSET_EMPTY)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2036 lj_trace_err(as->J, LJ_TRERR_NYICOAL);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2037 ra_rename(as, rset_pickbot(live & RSET_FPR), rset_pickbot(tmpset));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2038 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2039 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2040 /* Continue with coalescing to fix up the broken cycle(s). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2041 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2042
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2043 /* Inherit top stack slot already checked by parent trace. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2044 as->T->topslot = as->parent->topslot;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2045 if (as->topslot > as->T->topslot) { /* Need to check for higher slot? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2046 #ifdef EXITSTATE_CHECKEXIT
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2047 /* Highest exit + 1 indicates stack check. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2048 ExitNo exitno = as->T->nsnap;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2049 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2050 /* Reuse the parent exit in the context of the parent trace. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2051 ExitNo exitno = as->J->exitno;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2052 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2053 as->T->topslot = (uint8_t)as->topslot; /* Remember for child traces. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2054 asm_stack_check(as, as->topslot, irp, pallow, exitno);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2055 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2056 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2057
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2058 /* -- Tail of trace ------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2059
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2060 /* Get base slot for a snapshot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2061 static BCReg asm_baseslot(ASMState as, SnapShot snap, int *gotframe)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2062 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2063 SnapEntry *map = &as->T->snapmap[snap->mapofs];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2064 MSize n;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2065 for (n = snap->nent; n > 0; n--) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2066 SnapEntry sn = map[n-1];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2067 if ((sn & SNAP_FRAME)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2068 *gotframe = 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2069 return snap_slot(sn) - LJ_FR2;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2070 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2071 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2072 return 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2073 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2074
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2075 /* Link to another trace. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2076 static void asm_tail_link(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2077 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2078 SnapNo snapno = as->T->nsnap-1; /* Last snapshot. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2079 SnapShot *snap = &as->T->snap[snapno];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2080 int gotframe = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2081 BCReg baseslot = asm_baseslot(as, snap, &gotframe);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2082
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2083 as->topslot = snap->topslot;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2084 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2085 ra_allocref(as, REF_BASE, RID2RSET(RID_BASE));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2086
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2087 if (as->T->link == 0) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2088 /* Setup fixed registers for exit to interpreter. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2089 const BCIns *pc = snap_pc(&as->T->snapmap[snap->mapofs + snap->nent]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2090 int32_t mres;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2091 if (bc_op(pc) == BC_JLOOP) { / NYI: find a better way to do this. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2092 BCIns retpc = &traceref(as->J, bc_d(pc))->startins;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2093 if (bc_isret(bc_op(*retpc)))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2094 pc = retpc;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2095 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2096 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2097 emit_loadu64(as, RID_LPC, u64ptr(pc));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2098 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2099 ra_allockreg(as, i32ptr(J2GG(as->J)->dispatch), RID_DISPATCH);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2100 ra_allockreg(as, i32ptr(pc), RID_LPC);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2101 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2102 mres = (int32_t)(snap->nslots - baseslot - LJ_FR2);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2103 switch (bc_op(*pc)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2104 case BC_CALLM: case BC_CALLMT:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2105 mres -= (int32_t)(1 + LJ_FR2 + bc_a(pc) + bc_c(pc)); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2106 case BC_RETM: mres -= (int32_t)(bc_a(pc) + bc_d(pc)); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2107 case BC_TSETM: mres -= (int32_t)bc_a(*pc); break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2108 default: if (bc_op(*pc) < BC_FUNCF) mres = 0; break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2109 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2110 ra_allockreg(as, mres, RID_RET); /* Return MULTRES or 0. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2111 } else if (baseslot) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2112 /* Save modified BASE for linking to trace with higher start frame. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2113 emit_setgl(as, RID_BASE, jit_base);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2114 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2115 emit_addptr(as, RID_BASE, 8*(int32_t)baseslot);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2116
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2117 if (as->J->ktrace) { /* Patch ktrace slot with the final GCtrace pointer. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2118 setgcref(IR(as->J->ktrace)[LJ_GC64].gcr, obj2gco(as->J->curfinal));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2119 IR(as->J->ktrace)->o = IR_KGC;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2120 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2121
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2122 /* Sync the interpreter state with the on-trace state. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2123 asm_stack_restore(as, snap);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2124
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2125 /* Root traces that add frames need to check the stack at the end. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2126 if (!as->parent && gotframe)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2127 asm_stack_check(as, as->topslot, NULL, as->freeset & RSET_GPR, snapno);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2128 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2129
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2130 /* -- Trace setup --------------------------------------------------------- */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2131
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2132 /* Clear reg/sp for all instructions and add register hints. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2133 static void asm_setup_regsp(ASMState *as)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2134 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2135 GCtrace *T = as->T;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2136 int sink = T->sinktags;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2137 IRRef nins = T->nins;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2138 IRIns ir, lastir;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2139 int inloop;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2140 #if LJ_TARGET_ARM
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2141 uint32_t rload = 0xa6402a64;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2142 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2143
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2144 ra_setup(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2145 #if LJ_TARGET_ARM64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2146 ra_setkref(as, RID_GL, (intptr_t)J2G(as->J));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2147 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2148
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2149 /* Clear reg/sp for constants. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2150 for (ir = IR(T->nk), lastir = IR(REF_BASE); ir < lastir; ir++) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2151 ir->prev = REGSP_INIT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2152 if (irt_is64(ir->t) && ir->o != IR_KNULL) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2153 #if LJ_GC64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2154 /* The false-positive of irt_is64() for ASMREF_L (REF_NIL) is OK here. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2155 ir->i = 0; /* Will become non-zero only for RIP-relative addresses. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2156 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2157 /* Make life easier for backends by putting address of constant in i. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2158 ir->i = (int32_t)(intptr_t)(ir+1);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2159 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2160 ir++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2161 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2162 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2163
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2164 /* REF_BASE is used for implicit references to the BASE register. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2165 lastir->prev = REGSP_HINT(RID_BASE);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2166
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2167 as->snaprename = nins;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2168 as->snapref = nins;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2169 as->snapno = T->nsnap;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2170 as->snapalloc = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2171
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2172 as->stopins = REF_BASE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2173 as->orignins = nins;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2174 as->curins = nins;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2175
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2176 /* Setup register hints for parent link instructions. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2177 ir = IR(REF_FIRST);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2178 if (as->parent) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2179 uint16_t *p;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2180 lastir = lj_snap_regspmap(as->J, as->parent, as->J->exitno, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2181 if (lastir - ir > LJ_MAX_JSLOTS)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2182 lj_trace_err(as->J, LJ_TRERR_NYICOAL);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2183 as->stopins = (IRRef)((lastir-1) - as->ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2184 for (p = as->parentmap; ir < lastir; ir++) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2185 RegSP rs = ir->prev;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2186 p++ = (uint16_t)rs; / Copy original parent RegSP to parentmap. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2187 if (!ra_hasspill(regsp_spill(rs)))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2188 ir->prev = (uint16_t)REGSP_HINT(regsp_reg(rs));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2189 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2190 ir->prev = REGSP_INIT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2191 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2192 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2193
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2194 inloop = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2195 as->evenspill = SPS_FIRST;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2196 for (lastir = IR(nins); ir < lastir; ir++) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2197 if (sink) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2198 if (ir->r == RID_SINK)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2199 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2200 if (ir->r == RID_SUNK) { /* Revert after ASM restart. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2201 ir->r = RID_SINK;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2202 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2203 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2204 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2205 switch (ir->o) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2206 case IR_LOOP:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2207 inloop = 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2208 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2209 #if LJ_TARGET_ARM
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2210 case IR_SLOAD:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2211 if (!((ir->op2 & IRSLOAD_TYPECHECK) \|\| (ir+1)->o == IR_HIOP))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2212 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2213 /* fallthrough */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2214 case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2215 if (!LJ_SOFTFP && irt_isnum(ir->t)) break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2216 ir->prev = (uint16_t)REGSP_HINT((rload & 15));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2217 rload = lj_ror(rload, 4);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2218 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2219 case IR_TMPREF:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2220 if ((ir->op2 & IRTMPREF_OUT2) && as->evenspill < 4)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2221 as->evenspill = 4; /* TMPREF OUT2 needs two TValues on the stack. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2222 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2223 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2224 case IR_CALLXS: {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2225 CCallInfo ci;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2226 ci.flags = asm_callx_flags(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2227 ir->prev = asm_setup_call_slots(as, ir, &ci);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2228 if (inloop)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2229 as->modset \|= RSET_SCRATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2230 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2231 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2232 case IR_CALLL:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2233 /* lj_vm_next needs two TValues on the stack. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2234 #if LJ_TARGET_X64 && LJ_ABI_WIN
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2235 if (ir->op2 == IRCALL_lj_vm_next && as->evenspill < SPS_FIRST + 4)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2236 as->evenspill = SPS_FIRST + 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2237 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2238 if (SPS_FIRST < 4 && ir->op2 == IRCALL_lj_vm_next && as->evenspill < 4)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2239 as->evenspill = 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2240 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2241 /* fallthrough */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2242 case IR_CALLN: case IR_CALLA: case IR_CALLS: {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2243 const CCallInfo *ci = &lj_ir_callinfo[ir->op2];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2244 ir->prev = asm_setup_call_slots(as, ir, ci);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2245 if (inloop)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2246 as->modset \|= (ci->flags & CCI_NOFPRCLOBBER) ?
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2247 (RSET_SCRATCH & ~RSET_FPR) : RSET_SCRATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2248 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2249 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2250 case IR_HIOP:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2251 switch ((ir-1)->o) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2252 #if LJ_SOFTFP && LJ_TARGET_ARM
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2253 case IR_SLOAD: case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2254 if (ra_hashint((ir-1)->r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2255 ir->prev = (ir-1)->prev + 1;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2256 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2257 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2258 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2259 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2260 #if !LJ_SOFTFP && LJ_NEED_FP64 && LJ_32 && LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2261 case IR_CONV:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2262 if (irt_isfp((ir-1)->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2263 ir->prev = REGSP_HINT(RID_FPRET);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2264 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2265 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2266 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2267 /* fallthrough */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2268 case IR_CALLN: case IR_CALLL: case IR_CALLS: case IR_CALLXS:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2269 #if LJ_SOFTFP
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2270 case IR_MIN: case IR_MAX:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2271 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2272 (ir-1)->prev = REGSP_HINT(RID_RETLO);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2273 ir->prev = REGSP_HINT(RID_RETHI);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2274 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2275 default:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2276 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2277 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2278 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2279 #if LJ_SOFTFP
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2280 case IR_MIN: case IR_MAX:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2281 if ((ir+1)->o != IR_HIOP) break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2282 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2283 /* fallthrough */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2284 /* C calls evict all scratch regs and return results in RID_RET. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2285 case IR_SNEW: case IR_XSNEW: case IR_NEWREF: case IR_BUFPUT:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2286 if (REGARG_NUMGPR < 3 && as->evenspill < 3)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2287 as->evenspill = 3; /* lj_str_new and lj_tab_newkey need 3 args. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2288 #if LJ_TARGET_X86 && LJ_HASFFI
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2289 if (0) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2290 case IR_CNEW:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2291 if (ir->op2 != REF_NIL && as->evenspill < 4)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2292 as->evenspill = 4; /* lj_cdata_newv needs 4 args. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2293 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2294 /* fallthrough */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2295 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2296 /* fallthrough */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2297 case IR_CNEW:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2298 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2299 /* fallthrough */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2300 case IR_TNEW: case IR_TDUP: case IR_CNEWI: case IR_TOSTR:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2301 case IR_BUFSTR:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2302 ir->prev = REGSP_HINT(RID_RET);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2303 if (inloop)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2304 as->modset = RSET_SCRATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2305 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2306 case IR_STRTO: case IR_OBAR:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2307 if (inloop)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2308 as->modset = RSET_SCRATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2309 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2310 #if !LJ_SOFTFP
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2311 #if !LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2312 case IR_LDEXP:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2313 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2314 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2315 /* fallthrough */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2316 case IR_POW:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2317 if (!LJ_SOFTFP && irt_isnum(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2318 if (inloop)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2319 as->modset \|= RSET_SCRATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2320 #if LJ_TARGET_X86
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2321 if (irt_isnum(IR(ir->op2)->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2322 if (as->evenspill < 4) /* Leave room to call pow(). */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2323 as->evenspill = 4;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2324 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2325 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2326 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2327 ir->prev = REGSP_HINT(RID_FPRET);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2328 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2329 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2330 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2331 /* fallthrough / / for integer POW */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2332 case IR_DIV: case IR_MOD:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2333 if ((LJ_64 && LJ_SOFTFP) \|\| !irt_isnum(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2334 ir->prev = REGSP_HINT(RID_RET);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2335 if (inloop)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2336 as->modset \|= (RSET_SCRATCH & RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2337 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2338 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2339 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2340 #if LJ_64 && LJ_SOFTFP
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2341 case IR_ADD: case IR_SUB: case IR_MUL:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2342 if (irt_isnum(ir->t)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2343 ir->prev = REGSP_HINT(RID_RET);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2344 if (inloop)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2345 as->modset \|= (RSET_SCRATCH & RSET_GPR);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2346 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2347 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2348 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2349 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2350 case IR_FPMATH:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2351 #if LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2352 if (ir->op2 <= IRFPM_TRUNC) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2353 if (!(as->flags & JIT_F_SSE4_1)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2354 ir->prev = REGSP_HINT(RID_XMM0);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2355 if (inloop)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2356 as->modset \|= RSET_RANGE(RID_XMM0, RID_XMM3+1)\|RID2RSET(RID_EAX);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2357 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2358 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2359 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2360 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2361 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2362 if (inloop)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2363 as->modset \|= RSET_SCRATCH;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2364 #if LJ_TARGET_X86
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2365 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2366 #else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2367 ir->prev = REGSP_HINT(RID_FPRET);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2368 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2369 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2370 #if LJ_TARGET_X86ORX64
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2371 /* Non-constant shift counts need to be in RID_ECX on x86/x64. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2372 case IR_BSHL: case IR_BSHR: case IR_BSAR:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2373 if ((as->flags & JIT_F_BMI2)) /* Except if BMI2 is available. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2374 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2375 /* fallthrough */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2376 case IR_BROL: case IR_BROR:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2377 if (!irref_isk(ir->op2) && !ra_hashint(IR(ir->op2)->r)) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2378 IR(ir->op2)->r = REGSP_HINT(RID_ECX);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2379 if (inloop)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2380 rset_set(as->modset, RID_ECX);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2381 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2382 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2383 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2384 /* Do not propagate hints across type conversions or loads. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2385 case IR_TOBIT:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2386 case IR_XLOAD:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2387 #if !LJ_TARGET_ARM
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2388 case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2389 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2390 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2391 case IR_CONV:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2392 if (irt_isfp(ir->t) \|\| (ir->op2 & IRCONV_SRCMASK) == IRT_NUM \|\|
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2393 (ir->op2 & IRCONV_SRCMASK) == IRT_FLOAT)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2394 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2395 /* fallthrough */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2396 default:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2397 /* Propagate hints across likely 'op reg, imm' or 'op reg'. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2398 if (irref_isk(ir->op2) && !irref_isk(ir->op1) &&
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2399 ra_hashint(regsp_reg(IR(ir->op1)->prev))) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2400 ir->prev = IR(ir->op1)->prev;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2401 continue;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2402 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2403 break;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2404 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2405 ir->prev = REGSP_INIT;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2406 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2407 if ((as->evenspill & 1))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2408 as->oddspill = as->evenspill++;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2409 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2410 as->oddspill = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2411 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2412
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2413 /* -- Assembler core ------------------------------------------------------ */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2414
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2415 /* Assemble a trace. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2416 void lj_asm_trace(jit_State J, GCtrace T)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2417 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2418 ASMState as_;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2419 ASMState *as = &as_;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2420
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2421 /* Remove nops/renames left over from ASM restart due to LJ_TRERR_MCODELM. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2422 {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2423 IRRef nins = T->nins;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2424 IRIns *ir = &T->ir[nins-1];
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2425 if (ir->o == IR_NOP \|\| ir->o == IR_RENAME) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2426 do { ir--; nins--; } while (ir->o == IR_NOP \|\| ir->o == IR_RENAME);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2427 T->nins = nins;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2428 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2429 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2430
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2431 /* Ensure an initialized instruction beyond the last one for HIOP checks. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2432 /* This also allows one RENAME to be added without reallocating curfinal. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2433 as->orignins = lj_ir_nextins(J);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2434 lj_ir_nop(&J->cur.ir[as->orignins]);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2435
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2436 /* Setup initial state. Copy some fields to reduce indirections. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2437 as->J = J;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2438 as->T = T;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2439 J->curfinal = lj_trace_alloc(J->L, T); /* This copies the IR, too. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2440 as->flags = J->flags;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2441 as->loopref = J->loopref;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2442 as->realign = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2443 as->loopinv = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2444 as->parent = J->parent ? traceref(J, J->parent) : NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2445
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2446 /* Reserve MCode memory. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2447 as->mctop = as->mctoporig = lj_mcode_reserve(J, &as->mcbot);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2448 as->mcp = as->mctop;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2449 as->mclim = as->mcbot + MCLIM_REDZONE;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2450 asm_setup_target(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2451
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2452 /*
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2453 ** This is a loop, because the MCode may have to be (re-)assembled
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2454 ** multiple times:
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2455 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2456 ** 1. as->realign is set (and the assembly aborted), if the arch-specific
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2457 ** backend wants the MCode to be aligned differently.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2458 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2459 ** This is currently only the case on x86/x64, where small loops get
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2460 ** an aligned loop body plus a short branch. Not much effort is wasted,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2461 ** because the abort happens very quickly and only once.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2462 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2463 ** 2. The IR is immovable, since the MCode embeds pointers to various
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2464 ** constants inside the IR. But RENAMEs may need to be added to the IR
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2465 ** during assembly, which might grow and reallocate the IR. We check
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2466 ** at the end if the IR (in J->cur.ir) has actually grown, resize the
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2467 ** copy (in J->curfinal.ir) and try again.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2468 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2469 ** 95% of all traces have zero RENAMEs, 3% have one RENAME, 1.5% have
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2470 ** 2 RENAMEs and only 0.5% have more than that. That's why we opt to
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2471 ** always have one spare slot in the IR (see above), which means we
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2472 ** have to redo the assembly for only ~2% of all traces.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2473 **
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2474 ** Very, very rarely, this needs to be done repeatedly, since the
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2475 ** location of constants inside the IR (actually, reachability from
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2476 ** a global pointer) may affect register allocation and thus the
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2477 ** number of RENAMEs.
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2478 */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2479 for (;;) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2480 as->mcp = as->mctop;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2481 #ifdef LUA_USE_ASSERT
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2482 as->mcp_prev = as->mcp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2483 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2484 as->ir = J->curfinal->ir; /* Use the copied IR. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2485 as->curins = J->cur.nins = as->orignins;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2486
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2487 RA_DBG_START();
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2488 RA_DBGX((as, "===== STOP ====="));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2489
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2490 /* General trace setup. Emit tail of trace. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2491 asm_tail_prep(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2492 as->mcloop = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2493 as->flagmcp = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2494 as->topslot = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2495 as->gcsteps = 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2496 as->sectref = as->loopref;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2497 as->fuseref = (as->flags & JIT_F_OPT_FUSE) ? as->loopref : FUSE_DISABLED;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2498 asm_setup_regsp(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2499 if (!as->loopref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2500 asm_tail_link(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2501
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2502 /* Assemble a trace in linear backwards order. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2503 for (as->curins--; as->curins > as->stopins; as->curins--) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2504 IRIns *ir = IR(as->curins);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2505 /* 64 bit types handled by SPLIT for 32 bit archs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2506 lj_assertA(!(LJ_32 && irt_isint64(ir->t)),
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2507 "IR %04d has unsplit 64 bit type",
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2508 (int)(ir - as->ir) - REF_BIAS);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2509 asm_snap_prev(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2510 if (!ra_used(ir) && !ir_sideeff(ir) && (as->flags & JIT_F_OPT_DCE))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2511 continue; /* Dead-code elimination can be soooo easy. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2512 if (irt_isguard(ir->t))
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2513 asm_snap_prep(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2514 RA_DBG_REF();
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2515 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2516 asm_ir(as, ir);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2517 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2518
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2519 if (as->realign && J->curfinal->nins >= T->nins)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2520 continue; /* Retry in case only the MCode needs to be realigned. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2521
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2522 /* Emit head of trace. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2523 RA_DBG_REF();
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2524 checkmclim(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2525 if (as->gcsteps > 0) {
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2526 as->curins = as->T->snap[0].ref;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2527 asm_snap_prep(as); /* The GC check is a guard. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2528 asm_gc_check(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2529 as->curins = as->stopins;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2530 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2531 ra_evictk(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2532 if (as->parent)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2533 asm_head_side(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2534 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2535 asm_head_root(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2536 asm_phi_fixup(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2537
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2538 if (J->curfinal->nins >= T->nins) { /* IR didn't grow? */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2539 lj_assertA(J->curfinal->nk == T->nk, "unexpected IR constant growth");
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2540 memcpy(J->curfinal->ir + as->orignins, T->ir + as->orignins,
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2541 (T->nins - as->orignins) * sizeof(IRIns)); /* Copy RENAMEs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2542 T->nins = J->curfinal->nins;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2543 /* Fill mcofs of any unprocessed snapshots. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2544 as->curins = REF_FIRST;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2545 asm_snap_prev(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2546 break; /* Done. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2547 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2548
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2549 /* Otherwise try again with a bigger IR. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2550 lj_trace_free(J2G(J), J->curfinal);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2551 J->curfinal = NULL; /* In case lj_trace_alloc() OOMs. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2552 J->curfinal = lj_trace_alloc(J->L, T);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2553 as->realign = NULL;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2554 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2555
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2556 RA_DBGX((as, "===== START ===="));
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2557 RA_DBG_FLUSH();
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2558 if (as->freeset != RSET_ALL)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2559 lj_trace_err(as->J, LJ_TRERR_BADRA); /* Ouch! Should never happen. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2560
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2561 /* Set trace entry point before fixing up tail to allow link to self. */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2562 T->mcode = as->mcp;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2563 T->mcloop = as->mcloop ? (MSize)((char )as->mcloop - (char )as->mcp) : 0;
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2564 if (as->loopref)
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2565 asm_loop_tail_fixup(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2566 else
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2567 asm_tail_fixup(as, T->link); /* Note: this may change as->mctop! */
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2568 T->szmcode = (MSize)((char )as->mctop - (char )as->mcp);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2569 asm_snap_fixup_mcofs(as);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2570 #if LJ_TARGET_MCODE_FIXUP
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2571 asm_mcode_fixup(T->mcode, T->szmcode);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2572 #endif
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2573 lj_mcode_sync(T->mcode, as->mctoporig);
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2574 }
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2575
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2576 #undef IR
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2577
94705b5986b3 [ThirdParty] Added WRK and luajit for load testing. MrJuneJune <me@mrjunejune.com> parents: diff changeset	2578 #endif

Mercurial

annotate third_party/luajit/src/lj_asm.c @ 214:4c725fde6999